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1. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

2. 发明申请

US20100332762A1 DIRECTORY CACHE ALLOCATION BASED ON SNOOP RESPONSE INFORMATION 审中-公开
标题翻译：基于SNOOP响应信息的目录高速缓存分配
公开(公告)号：US20100332762A1
公开(公告)日：2010-12-30
申请号：US12495722
申请日：2009-06-30
申请人： Adrian C. Moga , Malcolm H. Mandviwalla , Stephen R. Van Doren
发明人： Adrian C. Moga , Malcolm H. Mandviwalla , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082
摘要： Methods and apparatus relating to directory cache allocation that is based on snoop response information are described. In one embodiment, an entry in a directory cache may be allocated for an address in response to a determination that another caching agent has a copy of the data corresponding to the address. Other embodiments are also disclosed.
摘要翻译：描述了基于窥探响应信息的与目录高速缓存分配有关的方法和装置。在一个实施例中，响应于确定另一高速缓存代理具有与该地址对应的数据的副本，可以为地址分配目录高速缓存中的条目。还公开了其他实施例。

3. 发明授权

US07203775B2 System and method for avoiding deadlock 有权
标题翻译：避免死锁的系统和方法
公开(公告)号：US07203775B2
公开(公告)日：2007-04-10
申请号：US10337833
申请日：2003-01-07
申请人： Stephen R. Van Doren , Gregory E. Tierney
发明人： Stephen R. Van Doren , Gregory E. Tierney
IPC分类号： G06F3/00
CPC分类号： G06F9/524
摘要： A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.
摘要翻译：系统和方法通过在主存储器中提供虚拟缓冲区来避免计算机系统中的死循环，例如循环路由死锁。计算机系统具有将具有访问主存储器的多个处理器耦合的互连网络。互连网络包括一个或多个路由代理，每个路由代理具有至少一个用于存储要转发的分组的缓冲器。当路由代理的缓冲区变满时，路由代理将至少一个数据包传输到虚拟缓冲区中。通过将数据包从缓冲区传送出去，路由代理释放了允许它接受新数据包的空间。如果新接受的分组也导致缓冲区变满，则另一分组被传送到虚拟缓冲器中。重复该过程，直到死锁状态得到解决。然后从虚拟缓冲区中检索数据包。

4. 发明授权

US06286090B1 Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches 失效
标题翻译：选择性地强制页表提取之间的干扰顺序和相应数据提取的机制
公开(公告)号：US06286090B1
公开(公告)日：2001-09-04
申请号：US09084621
申请日：1998-05-26
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
IPC分类号： G06F1200
CPC分类号： G06F12/1054 , G06F12/0813
摘要： A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
摘要翻译：一种技术选择性地将由多处理器系统的处理器发出的存储器参考操作之间的参考间排序施加于与由翻译缓冲器（TB）错过流程程影响的页表项（PTE）相关的页面内的地址。 TB错误流被用于检索包含在PTE中的信息，用于将虚拟地址映射到物理地址，并且随后允许在映射的物理地址处检索数据。响应于存储器引用（读取）操作检索的PTE不会被加载到TB中，直到与该读取操作相关联的提交信号返回到处理器。一旦返回了PTE和相关联的提交信号，处理器将PTE加载到TB中，以便它可以用于针对物理地址的数据的后续读取操作。

5. 发明申请

US20150186275A1 Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
标题翻译：包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存
公开(公告)号：US20150186275A1
公开(公告)日：2015-07-02
申请号：US14142045
申请日：2013-12-27
申请人： Adrian C. Moga , Vedaraman Geetha , Bahaa Fahim , Robert G. Blankenship , Yen-Cheng Liu , Jeffrey D. Chamberlain , Stephen R. Van Doren
发明人： Adrian C. Moga , Vedaraman Geetha , Bahaa Fahim , Robert G. Blankenship , Yen-Cheng Liu , Jeffrey D. Chamberlain , Stephen R. Van Doren
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0888
摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.
摘要翻译：描述了包括一个或多个处理核心的处理器。处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控制器。处理核心包括存储器控制器上方的多个缓存级别。处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。所述状态信息包括包含状态和不包含状态中的所选择的状态。包含状态表示在内存中存在高速缓存行的副本或版本。不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为在包容性状态。

6. 发明授权

US08090914B2 System and method for creating ordering points 有权
标题翻译：用于创建订购点的系统和方法
公开(公告)号：US08090914B2
公开(公告)日：2012-01-03
申请号：US10760652
申请日：2004-01-20
申请人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： A system comprises a first node operative to provide a source broadcast requesting data. The first node associates an F-state with a copy of the data in response to receiving the copy of the data from memory and receiving non-data responses from other nodes in the system. The non-data responses include an indication that at least a second node includes a shared copy of the data. The F-state enabling the first node to serve as an ordering point in the system capable of responding to requests from other nodes in the system with a shared copy of the data.
摘要翻译：系统包括用于提供源广播请求数据的第一节点。响应于从存储器接收数据的副本并从系统中的其他节点接收非数据响应，第一节点将F状态与数据的副本相关联。非数据响应包括至少第二节点包括数据的共享副本的指示。 F状态使得第一节点能够用作系统中能够利用数据的共享副本响应来自系统中其他节点的请求的系统中的订购点。

7. 发明授权

US07769959B2 System and method to facilitate ordering point migration to memory 失效
标题翻译：系统和方法，方便订单点迁移到内存
公开(公告)号：US07769959B2
公开(公告)日：2010-08-03
申请号：US10760599
申请日：2004-01-20
申请人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
发明人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
摘要翻译：系统可以包括包括数据的排序点的第一节点，第一节点可操作地采用与将数据写回到存储器相关联的回写事务。第一节点响应于由存储器提供的确认指示数据的排序点已经从第一节点迁移到存储器的系统中的至少一个其他节点广播回写消息。

8. 发明授权

US06892290B2 Linked-list early race resolution mechanism 有权
标题翻译：链接列表早期种族解析机制
公开(公告)号：US06892290B2
公开(公告)日：2005-05-10
申请号：US10263738
申请日：2002-10-03
申请人： Stephen R. Van Doren
发明人： Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0828
摘要： Early race conditions caused by multiple computer system entities issuing memory reference operations for a given memory block are resolved by creating linked lists identifying the entities. The lists are preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The MAF entries cooperate to form one or more read chains each of which links the entities requesting read access to a particular version of the given memory block. The MAF entries also cooperate to form a single write chain that links the entities requesting write access to the given memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in satisfying its obligations as part of the read and write chains, thereby ensuring that each entity receives the version of the given memory block that it desires.
摘要翻译：通过为给定的内存块发出内存引用操作的多个计算机系统实体引起的早期竞争条件通过创建标识实体的链表来解决。优选地通过将信息和状态存储在由实体维护的遗漏地址文件（MAF）条目中来形成。 MAF条目协作形成一个或多个读链，每个读链将请求读访问的实体链接到给定存储块的特定版本。 MAF条目还协作形成一个链接请求写访问的实体到给定的存储块的单个写链。当期望的存储器块变得可用时，存储在MAF条目中的信息和状态随后被每个实体用来满足其义务作为读取和写入链的一部分，从而确保每个实体接收给定存储器块的版本，它的愿望

9. 发明授权

US06801986B2 Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation 失效
标题翻译：在加载锁定/存储条件原子存储器操作期间，通过延迟所有权所有权投降来实现预防行为
公开(公告)号：US06801986B2
公开(公告)日：2004-10-05
申请号：US09933536
申请日：2001-08-20
申请人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
发明人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834
摘要： A method, for executing a load locked and a store conditional instruction in a processor, achieves an atomic read-write operation to a memory block. First the load locked instruction is executed to read a memory block, and the processor in response to executing the load locked instruction issues a read modify system command to read the block and to take ownership of the block by the processor, and also sets a lock flag for the address of the memory block, and writes a value of the memory block into a cache of the processor as a cache copy of the memory block. The lock flag, upon receipt of an invalidate message by the processor for the cache copy of the memory block, is reset if any invalidate messages for the memory block are received by the processor. The processor waits for a selected time interval before the processor surrenders ownership of the memory block upon receipt of an ownership request message, if any is received by the processor after execution of the load locked instruction. The processor executes the store conditional instruction, and the processor in response to executing the store conditional instruction tests the lock flag, and if the lock flag is set, writing to the cache copy of the memory block. The processor ends, in the event that the lock flag is reset, the store conditional instruction and does not write to the cache copy of the memory block.
摘要翻译：一种用于在处理器中执行加载锁定和存储条件指令的方法，对存储器块实现原子读写操作。首先执行加载锁定指令以读取存储器块，并且响应于执行加载锁定指令的处理器发出读取修改系统命令来读取块并由处理器获取块的所有权，并且还设置锁定标记存储器块的地址，并将存储器块的值写入处理器的高速缓存作为存储器块的高速缓存副本。如果处理器接收到存储块的任何无效消息，则锁定标志在由处理器接收到存储器块的高速缓存副本的无效消息时被重置。处理器在接收到所有权请求消息之后处理器递交所述存储器块的所有权，等待处理器选定的时间间隔（如果在执行加载锁定指令之后由处理器接收到）。处理器执行存储条件指令，并且处理器响应于执行存储条件指令测试锁定标志，并且如果设置了锁定标志，则写入存储器块的高速缓存副本。处理器在锁定标志被复位的情况下结束，存储条件指令，并且不写入存储器块的高速缓存副本。

10. 发明授权

US06209065B1 Mechanism for optimizing generation of commit-signals in a distributed shared-memory system 失效
标题翻译：优化分布式共享内存系统中提交信号生成的机制
公开(公告)号：US06209065B1
公开(公告)日：2001-03-27
申请号：US08957230
申请日：1997-10-24
申请人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
发明人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
IPC分类号： G06F1314
CPC分类号： G06F9/542 , G06F9/52
摘要： A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The mechanism generally comprises a structure that indicates whether the memory reference operation affects other processors of other nodes of the multiprocessor system. An ordering point of the local node generates an optimized commit-signal when the structure indicates that the memory reference operation does not affect the other processors.
摘要翻译：一种机制响应于处理器向具有用于互连多个节点的分层交换机的多处理器系统的本地节点发出的存储器参考操作来优化多处理器系统的控制逻辑的生成提交信号。该机制通常包括指示存储器参考操作是否影响多处理器系统的其他节点的其他处理器的结构。当结构指示存储器参考操作不影响其他处理器时，本地节点的排序点生成优化的提交信号。

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