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1. 发明申请

US20100052826A1 ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY 有权
标题翻译：隔离器配有相应的可配置存储器
公开(公告)号：US20100052826A1
公开(公告)日：2010-03-04
申请号：US12494618
申请日：2009-06-30
申请人： PHIL A. CALLAHAN , AHSAN JAVED , ZHIWEI DONG , AXEL THOMSEN , DONALD E. ALFANO , TIMOTHY DUPUIS , KA Y. LEUNG
发明人： PHIL A. CALLAHAN , AHSAN JAVED , ZHIWEI DONG , AXEL THOMSEN , DONALD E. ALFANO , TIMOTHY DUPUIS , KA Y. LEUNG
IPC分类号： H03H2/00
CPC分类号： H01L24/48 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L23/642 , H01L23/66 , H01L24/06 , H01L24/49 , H01L25/0655 , H01L2223/6611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H04B2203/5491 , H01L2224/45099 , H01L2924/00
摘要： An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary.
摘要翻译：一种隔离器，其包括彼此电隔离的第一和第二基本相同的电路，并且每个具有至少一个用于在其间的隔离边界传送信号的通信信道，所述第一和第二电路中的每一个具有与其操作相关联的可配置功能。提供耦合装置用于在第一和第二电路的至少一个通信信道之间的隔离边界上耦合信号。提供第一和第二配置存储器，每个与第一和第二电路中的相应一个相关联。提供第一和第二配置控制设备，每个配置控制设备与第一和第二电路中的相应一个相关联，并且每个配置控制设备配置第一和第二电路中相关联的一个的功能。第一和第二可配置存储器在其中存储有互补配置信息，以控制第一和第二电路的每个功能以互补的方式进行操作，用于跨越隔离边界的信号通信。

2. 发明申请

US20090027243A1 MCU WITH INTEGRATED VOLTAGE ISOLATOR TO PROVIDE A GALVANIC ISOLATION BETWEEN INPUT AND OUTPUT 有权
标题翻译：具有集成电压隔离器的MCU提供输入和输出之间的隔离隔离
公开(公告)号：US20090027243A1
公开(公告)日：2009-01-29
申请号：US12164998
申请日：2008-06-30
申请人： KA Y. LEUNG , DONALD E. ALFANO , DAVID P. BRESEMANN
发明人： KA Y. LEUNG , DONALD E. ALFANO , DAVID P. BRESEMANN
IPC分类号： H03M9/00
CPC分类号： H01L23/66 , H01L23/48 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/45099
摘要： An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit.
摘要翻译：集成电路包括位于第一管芯上的第一微控制器单元。第一微控制器单元包括用于提供并行数据流的第一处理核心。第二微控制器单元位于第二管芯上，并且包括用于接收并行数据流的第二处理核。电压隔离电路以串行数据流从第一微控制器和第二微控制器之间的并行数据流传输数据，并在第一微控制器单元和第二微控制器单元之间提供电隔离。

3. 发明申请

US20080267301A1 BIDIRECTIONAL MULTIPLEXED RF ISOLATOR 有权
标题翻译：双向多路射频隔离器
公开(公告)号：US20080267301A1
公开(公告)日：2008-10-30
申请号：US11772178
申请日：2007-06-30
申请人： DONALD E. ALFANO , BRETT ETTER , TIMOTHY DUPUIS
发明人： DONALD E. ALFANO , BRETT ETTER , TIMOTHY DUPUIS
IPC分类号： H04B3/00
CPC分类号： H01L23/66 , H01L23/48 , H01L23/49503 , H01L23/4952 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48464 , H01L2224/49171 , H01L2224/49175 , H01L2224/49176 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/01083 , H01L2924/1204 , H01L2924/12041 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H03K5/135 , H03M9/00 , H04B3/542 , H04B3/56 , H04B2203/542 , H04L5/14 , H04L25/0268 , H01L2924/00 , H01L2224/45099
摘要： An integrated circuit single chip isolator provides bidirectional data transfer for a plurality of communications channels. A first and second dies are located on a first and second sides of a voltage isolation barrier in the chip and have a first and second plurality of digital data input/output pins associated therewith. First circuitry located on the first die on a first side of the voltage isolation barrier and third circuitry located on the second die on a second side of the voltage isolation barrier serializes a plurality of parallel digital data inputs from the associated plurality of digital data input/output pins onto a one link across the voltage isolation barrier and transmits synchronization clock signals associated with the plurality of digital data inputs over a another link across the voltage isolation barrier. Second circuitry located on the second die on a second side of the voltage isolation barrier and fourth circuitry located on the first die on a first side of the voltage isolation barrier de-serializes the first plurality of digital data inputs from the first link onto the second plurality of digital data input/output pins and receives the first synchronization clock signal associated with the plurality of digital data inputs on the second link. Switches associated with each of the plurality of input/output pins between transmit and receive circuitry.
摘要翻译：集成电路单芯片隔离器为多个通信信道提供双向数据传输。第一和第二管芯位于芯片中的电压隔离屏障的第一和第二侧上，并且具有与其相关联的第一和第二多个数字数据输入/输出引脚。位于电压隔离屏障的第一侧上的第一管芯上的第一电路和位于电压隔离栅极的第二侧上的第二管芯上的第三电路将多个并行的数字数据输入从相关的多个数字数据输入/ 输出引脚跨越电压隔离屏障的一个链路，并且跨越电压隔离屏障在另一个链路上发送与多个数字数据输入相关联的同步时钟信号。位于电压隔离屏障的第二侧上的第二管芯上的第二电路和位于电压隔离栅极的第一侧上的第一管芯上的第四电路将第一多个数字数据输入从第一链路反序列化到第二管多个数字数据输入/输出引脚，并且接收与第二链路上的多个数字数据输入相关联的第一同步时钟信号。与发送和接收电路之间的多个输入/输出引脚中的每一个相关联的开关。

4. 发明申请

US20080082716A1 BUS TO MCU BRIDGE 有权
标题翻译：总线到单片机桥
公开(公告)号：US20080082716A1
公开(公告)日：2008-04-03
申请号：US11537452
申请日：2006-09-29
申请人： DONALD E. ALFANO
发明人： DONALD E. ALFANO
IPC分类号： G06F13/20
CPC分类号： G06F13/4022
摘要： An integrated circuit enables interconnection of a serial digital bus with a microcontroller unit. A physical interface provides for the transmission and reception of messages over the serial digital bus. A communication interface includes a serial interface for communicating with the microcontroller unit. The communication's interface further extracts clock data and information data from the received messages from the serial data bus in a format that may be transmitted to the microcontroller unit via the serial interface. The communication interface further formats data received from the serial interface into messages for transmission onto the serial digital bus. A sync timing generator generates a sync pulse for synchronizing the microcontroller unit with the serial interface of the communication interface.
摘要翻译：集成电路使串行数字总线与微控制器单元互连。物理接口通过串行数字总线提供消息的发送和接收。通信接口包括用于与微控制器单元通信的串行接口。通信接口还从串行数据总线的接收到的消息中提取时钟数据和信息数据，格式可以通过串行接口发送到微控制器单元。通信接口进一步将从串行接口接收的数据格式化成用于传输到串行数字总线的消息。同步定时发生器产生用于使微控制器单元与通信接口的串行接口同步的同步脉冲。

5. 发明申请

US20080155289A1 MICRO CONTROLLER UNIT (MCU) WITH RTC 有权
标题翻译：微控制器单元（MCU）与RTC
公开(公告)号：US20080155289A1
公开(公告)日：2008-06-26
申请号：US12046321
申请日：2008-03-11
申请人： KENNETH W. FERNALD , DONALD E. ALFANO
发明人： KENNETH W. FERNALD , DONALD E. ALFANO
IPC分类号： G06F1/32 , G06F1/14
CPC分类号： G06F1/3203
摘要： A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.
摘要翻译：公开了具有独立实时时钟（RTC）的微控制器单元（MCU）。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。主时钟电路为处理电路提供定时。电源控制电路控制处理电路和主时钟电路的电源，以控制其工作在至少全功率模式下工作，从供电电压输入和低功耗模式绘制小于全功率模式功率电平从电源电压输入。还提供独立的RTC电路，独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。由RTC时钟电路计时钟的定时器可操作以增加存储的时间值以便从其输出，RTC时钟电路具有确定的时基。输入/输出（I / O）设备提供处理电路对定时器输出的结果的访问。电源管理电路管理独立RTC电路的电源，使得RTC时钟电路，定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。

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