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1. 发明授权

US08860140B2 Tunneling field effect transistor and method for forming the same 有权
标题翻译：隧道场效应晶体管及其形成方法
公开(公告)号：US08860140B2
公开(公告)日：2014-10-14
申请号：US13147470
申请日：2011-06-24
申请人： Renrong Liang , Ning Cui , Jing Wang , Jun Xu
发明人： Renrong Liang , Ning Cui , Jing Wang , Jun Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L29/49 , H01L29/739
CPC分类号： H01L29/7391 , H01L29/4908 , H01L29/4983 , H01L29/66356
摘要： The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.
摘要翻译：本公开提供了一种TFET，其包括：基板; 形成在所述衬底中的沟道区，以及形成在所述沟道区的两侧的源极区和漏极区; 形成在所述沟道区上的栅极叠层，其中所述栅极堆叠包括：栅极电介质层，以及至少第一栅极电极和第二栅极电极，所述栅极电极和第二栅极电极沿着从所述源极区域到所述漏极区域的方向分布并形成在所述栅极电介质上第一栅电极和第二栅电极具有不同的功函数; 以及分别形成在第一栅电极的一侧和第二栅极侧的第一侧壁和第二侧壁。

2. 发明授权

US09059268B2 Tunneling field effect transistor and method for fabricating the same 有权
标题翻译：隧道场效应晶体管及其制造方法
公开(公告)号：US09059268B2
公开(公告)日：2015-06-16
申请号：US13641116
申请日：2012-08-21
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265 , H01L29/739 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/51
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/0649 , H01L29/0834 , H01L29/0847 , H01L29/42368 , H01L29/517 , H01L29/66356 , H01L29/66477 , H01L29/7391 , H01L29/7843
摘要： A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, the first buried layer being first type non-heavily-doped, and the second buried layer being second type non-heavily-doped; a source region and a drain region formed in the semiconductor substrate and located on the first buried layer and the second buried layer respectively; and a gate dielectric layer formed on the one or more isolation structures, and a gate formed on the gate dielectric layer.
摘要翻译：提供隧道场效应晶体管及其制造方法。隧道场效应晶体管包括：半导体衬底; 形成在所述半导体衬底中的沟道区，其中形成在所述沟道区中的一个或多个隔离结构; 第一掩埋层和第二掩埋层，形成在所述半导体衬底中并且分别位于所述沟道区的两侧，所述第一掩埋层是第一类型非重掺杂的，所述第二掩埋层是第二类型非重掺杂的，掺杂; 源极区域和漏极区域，形成在所述半导体衬底中，分别位于所述第一掩埋层和所述第二掩埋层上; 以及形成在所述一个或多个隔离结构上的栅极电介质层，以及形成在所述栅极介电层上的栅极。

3. 发明授权

US08853674B2 Tunneling field effect transistor structure and method for forming the same 有权
标题翻译：隧道场效应晶体管结构及其形成方法
公开(公告)号：US08853674B2
公开(公告)日：2014-10-07
申请号：US13640929
申请日：2012-08-28
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/775 , H01L29/786 , H01L29/739
CPC分类号： H01L29/78603 , H01L29/7391
摘要： A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.
摘要翻译：提供隧道场效应晶体管结构及其形成方法。隧道场效应晶体管结构包括：衬底; 形成在所述基板上的多个凸起结构，每两个相邻的凸起结构被宽度小于30nm的预定空腔隔开，所述凸结构包括多组，并且每组包括多于两个凸结构; 形成在凸结构的顶部上的多个浮膜，每个悬浮膜对应于一组凸结构，每个浮动膜的与每组中的中间凸结构的顶部相对应的区域形成为沟道区，以及在沟道区两侧的每个浮膜的区域分别形成为具有相反导电类型的源极区域和漏极区域; 以及形成在每个通道区域上的栅极堆叠。

4. 发明授权

US08815690B2 Tunneling device and method for forming the same 有权
标题翻译：隧道装置及其形成方法
公开(公告)号：US08815690B2
公开(公告)日：2014-08-26
申请号：US13147465
申请日：2011-06-24
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/42312 , H01L21/26586 , H01L29/66356 , H01L29/7391
摘要： The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.
摘要翻译：本公开提供一种隧道装置，其包括：基板; 形成在所述基板中的沟道区域，以及形成在所述沟道区域的两侧的源极区域和漏极区域; 以及形成在所述沟道区上的栅极堆叠以及形成在所述栅极堆叠的两侧上的第一侧壁和第二侧壁，其中所述栅极堆叠包括：第一栅极介电层; 形成在所述第一栅极介电层上的至少第一栅电极和第二栅电极; 形成在所述第一栅电极和所述第一侧壁之间的第二栅介质层; 以及形成在第二栅电极和第二侧壁之间的第三栅介质层。

5. 发明授权

US08653574B2 Flash memory and method for fabricating the same 有权
标题翻译：闪存及其制造方法
公开(公告)号：US08653574B2
公开(公告)日：2014-02-18
申请号：US13514591
申请日：2012-05-22
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/76
CPC分类号： H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gate formed on the gate dielectric.
摘要翻译：提供闪速存储器及其制造方法。闪存包括：半导体衬底; 在半导体衬底上形成的存储介质层，包括从底部到顶部：隧道氧化物层，氮化硅层和阻挡氧化物层; 形成在所述存储介质层上的半导体层，分别包括位于所述沟道区两侧的沟道区和源极区和漏极区; 以及形成在沟道区上并包括形成在栅极电介质上的栅极电介质和栅极的栅极堆叠。

6. 发明申请

US20130181185A1 TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：隧道场效应晶体管及其制造方法
公开(公告)号：US20130181185A1
公开(公告)日：2013-07-18
申请号：US13695341
申请日：2012-09-06
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/517 , H01L29/66356 , H01L29/66666 , H01L29/7391
摘要： A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.
摘要翻译：提供隧道场效应晶体管及其制造方法。隧道场效应晶体管包括：形成在半导体衬底中的半导体衬底和漏极层，其中漏极层是第一类型重掺杂的; 形成在所述漏极层上的外延层，在所述外延层中形成隔离区; 形成在外延层中的掩埋层，其中所述掩埋层是第二类型轻掺杂的; 在掩埋层中形成的源，其中源极重掺杂; 形成在所述外延层上的栅极电介质层和形成在所述栅极介电层上的栅极; 以及形成在源极上的源极金属接触层和形成在漏极层下面的漏极金属接触层。

7. 发明申请

US20130105764A1 TUNNELING FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：隧道场效应晶体管结构及其形成方法
公开(公告)号：US20130105764A1
公开(公告)日：2013-05-02
申请号：US13640929
申请日：2012-08-28
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/78603 , H01L29/7391
摘要： A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.
摘要翻译：提供隧道场效应晶体管结构及其形成方法。隧道场效应晶体管结构包括：衬底; 形成在所述基板上的多个凸起结构，每两个相邻的凸起结构被宽度小于30nm的预定空腔隔开，所述凸结构包括多组，并且每组包括多于两个凸结构; 形成在凸结构的顶部上的多个浮膜，每个悬浮膜对应于一组凸结构，每个浮动膜的与每组中的中间凸结构的顶部相对应的区域形成为沟道区，以及在沟道区两侧的每个浮膜的区域分别形成为具有相反导电类型的源极区域和漏极区域; 以及形成在每个通道区域上的栅极堆叠。

8. 发明申请

US20120223387A1 TUNNELING DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：隧道装置及其形成方法
公开(公告)号：US20120223387A1
公开(公告)日：2012-09-06
申请号：US13147465
申请日：2011-06-24
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/42312 , H01L21/26586 , H01L29/66356 , H01L29/7391
摘要： The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.
摘要翻译：本公开提供一种隧道装置，其包括：基板; 形成在所述衬底中的沟道区，以及形成在所述沟道区的两侧的源极区和漏极区; 以及形成在所述沟道区上的栅极堆叠以及形成在所述栅极堆叠的两侧上的第一侧壁和第二侧壁，其中所述栅极堆叠包括：第一栅极介电层; 形成在所述第一栅极介电层上的至少第一栅电极和第二栅电极; 形成在所述第一栅电极和所述第一侧壁之间的第二栅介质层; 以及形成在第二栅电极和第二侧壁之间的第三栅介质层。

9. 发明授权

US08803225B2 Tunneling field effect transistor having a lightly doped buried layer 有权
标题翻译：具有轻掺杂掩埋层的隧穿场效应晶体管
公开(公告)号：US08803225B2
公开(公告)日：2014-08-12
申请号：US13695341
申请日：2012-09-06
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7827 , H01L29/517 , H01L29/66356 , H01L29/66666 , H01L29/7391
摘要： A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.
摘要翻译：提供隧道场效应晶体管及其制造方法。隧道场效应晶体管包括：半导体衬底和形成在半导体衬底中的漏极层，其中漏极层是重掺杂的第一类型; 形成在所述漏极层上的外延层，在所述外延层中形成隔离区; 形成在外延层中的掩埋层，其中所述掩埋层是第二类型轻掺杂的; 在掩埋层中形成的源，其中源极重掺杂; 形成在所述外延层上的栅极电介质层和形成在所述栅极介电层上的栅极; 以及形成在源极上的源极金属接触层和形成在漏极层下面的漏极金属接触层。

10. 发明申请

US20130207173A1 FLASH MEMORY AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：闪存及其制造方法
公开(公告)号：US20130207173A1
公开(公告)日：2013-08-15
申请号：US13514591
申请日：2012-05-22
申请人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
发明人： Ning Cui , Renrong Liang , Jing Wang , Jun Xu
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A flash memory and a method for fabricating the same are provided. The flash memory comprises: a semiconductor substrate; a storage medium layer formed on the semiconductor substrate and comprising from bottom to top: a tunneling oxide layer, a silicon nitride layer and a blocking oxide layer; a semiconductor layer formed on the storage medium layer and comprising a channel region and a source region and a drain region located on both sides of the channel region respectively; and a gate stack formed on the channel region and comprising a gate dielectric and a gateformed on the gate dielectric.
摘要翻译：提供闪速存储器及其制造方法。闪存包括：半导体衬底; 在半导体衬底上形成的存储介质层，包括从底部到顶部：隧道氧化物层，氮化硅层和阻挡氧化物层; 形成在所述存储介质层上的半导体层，分别包括位于所述沟道区两侧的沟道区和源极区和漏极区; 以及栅极堆叠，其形成在沟道区上并且包括栅极电介质和栅极形成在栅极电介质上。

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