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1. 发明授权

US06363408B1 Method and apparatus for summing selected bits from a plurality of machine vectors 有权
标题翻译：用于对来自多个机器向量的所选位进行求和的方法和装置
公开(公告)号：US06363408B1
公开(公告)日：2002-03-26
申请号：US09183084
申请日：1998-10-30
申请人： Umair A. Khan , Nazar A. Zaidi
发明人： Umair A. Khan , Nazar A. Zaidi
IPC分类号： G06F750
CPC分类号： G06F7/764 , G06F7/509
摘要： An apparatus is provided for adding selected bits. The apparatus includes a hardware device having a plurality of ordered input terminals to receive binary signals for a portion of an ordered set of the selected bits. The hardware device also has a plurality of output terminals to transmit digital signals for a plurality of sums. Each sum adds a set of speculative values of a portion of the selected bits. A method is provided for adding a set of ordered selected logic signals. The method includes producing a set of digital signals for a plurality of sums and selecting one of the digital signals for a sum in response to receiving a signal for a correction vector. Each sum adds a set of speculative values for an ordered set of selected logic signals. The selected sum is equal to a sum of speculative values of the selected logic signals as identified by the correction vector. The method also includes transmitting the selected one of the digital signals to an output terminal.
摘要翻译：提供了用于添加所选位的装置。该装置包括具有多个有序输入端的硬件设备，用于接收所选位的有序集合的一部分的二进制信号。硬件设备还具有多个输出端子，用于传送多个和的数字信号。每个和添加一组所选位的一部分的推测值。提供了一种用于添加一组有序选择的逻辑信号的方法。该方法包括产生用于多个和的一组数字信号，并且响应于接收到用于校正矢量的信号而选择一个数字信号作为和。每个和添加一组有选择的逻辑信号的有序集合的推测值。所选择的和等于由校正矢量识别的所选逻辑信号的推测值之和。该方法还包括将所选择的一个数字信号发送到输出端。

2. 发明授权

US06292882B1 Method and apparatus for filtering valid information for downstream processing 有权
标题翻译：用于过滤下游处理有效信息的方法和装置
公开(公告)号：US06292882B1
公开(公告)日：2001-09-18
申请号：US09209094
申请日：1998-12-10
申请人： Nazar A. Zaidi , Umair A. Khan
发明人： Nazar A. Zaidi , Umair A. Khan
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3017
摘要： In one aspect, the invention includes an apparatus for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data lines of a buffer. The apparatus includes a filter for filtering instructions within a digital system. The filter includes an address generator capable of generating at least two addresses in response to receiving at least two micro-operations. The filter also includes a logic circuit coupled to the address generator. The logic circuit filters addresses corresponding to valid micro-operations in response to assessing the state of a portion of each of the micro-operations. In a second aspect, the invention includes a method for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data lines of a buffer. The method includes, generating at least two addresses in response to receiving at least two micro-operations. The method further includes filtering addresses corresponding to valid micro-operations in response to assessing the state of a portion of each of the micro-operations.
摘要翻译：在一个方面，本发明包括用于对数字系统内的指令进行滤波的装置，其消除了将有效指令物理地切换到缓冲器的连续数据线上的需要。该装置包括用于过滤数字系统内的指令的滤波器。该滤波器包括能够响应于接收至少两个微操作而产生至少两个地址的地址发生器。滤波器还包括耦合到地址发生器的逻辑电路。响应于评估每个微操作的一部分的状态，逻辑电路对与有效微操作相对应的地址进行滤波。在第二方面，本发明包括一种用于过滤数字系统内的指令的方法，该方法消除了将有效指令物理地切换到缓冲器的连续数据线上的需要。该方法包括响应于接收至少两个微操作而产生至少两个地址。该方法还包括响应于评估每个微操作的一部分的状态来过滤对应于有效微操作的地址。

3. 发明授权

US06405307B1 Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipeline 失效
标题翻译：在指令提取流水线中检测和处理自修改代码冲突的装置和方法
公开(公告)号：US06405307B1
公开(公告)日：2002-06-11
申请号：US09088634
申请日：1998-06-02
申请人： Keshavram N. Murty , Nazar A. Zaidi
发明人： Keshavram N. Murty , Nazar A. Zaidi
IPC分类号： G06F922
CPC分类号： G06F9/3812 , G06F9/3861 , G06F9/3867
摘要： A system and method are described for detecting and recovering from self-modifying code (SMC) conflicts. In one embodiment, detection is accomplished by accessing the contents of a memory, configured to contain a number of recently executed instructions, to obtain an address. This address is compared to information propagating through a front-end pipeline of an instruction pipeline. The instruction pipeline includes the front-end pipeline to support loading and propagation of information through the instruction pipeline and a back-end pipeline to support execution of instructions along with writeback to the memory. If the address matches the information propagating through the front-end pipeline, a SMC conflict has occurred and at least some of the pipelined information is invalidated.
摘要翻译：描述了用于从自修改代码（SMC）冲突检测和恢复的系统和方法。在一个实施例中，通过访问被配置为包含多个最近执行的指令的存储器的内容来获得地址来实现检测。该地址与通过指令流水线的前端流水线传播的信息进行比较。指令流水线包括前端流水线，以支持通过指令流水线加载和传播信息，以及后端流水线，以支持执行指令以及向存储器写回。如果地址匹配通过前端流水线传播的信息，则发生SMC冲突，并且至少部分流水线信息无效。

4. 发明授权

US5961630A Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency 失效
标题翻译：通过使用后备用延迟来处理动态结构危害和异常的方法和装置
公开(公告)号：US5961630A
公开(公告)日：1999-10-05
申请号：US1170
申请日：1997-12-30
申请人： Nazar A. Zaidi , Michael J. Morrison , Elango Ganesan
发明人： Nazar A. Zaidi , Michael J. Morrison , Elango Ganesan
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.
摘要翻译：一种通过使用后备用延迟来处理动态结构危害和例外的方法，包括：接收多个指令; 选择执行可能导致异常的第一条指令; 将后准备延迟分配给遵循所述第一指令的第二指令; 以及将与第一指令分离的第一指令和第二指令的执行调度至少等于第二指令的就绪后等待时间的时间量。

5. 发明授权

US06216221B1 Method and apparatus for expanding instructions 失效
标题翻译：用于扩展指令的方法和装置
公开(公告)号：US06216221B1
公开(公告)日：2001-04-10
申请号：US09001741
申请日：1997-12-31
申请人： Nazar A. Zaidi , Michael J. Morrison , Bharat Zaveri
发明人： Nazar A. Zaidi , Michael J. Morrison , Bharat Zaveri
IPC分类号： G06F1338
CPC分类号： G06F9/382 , G06F9/30043 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： A microprocessor includes a decoder, a queue, and a renamer. The decoder is adapted to receive a program instruction and decode the program instruction to provide a first decoded instruction. The first decoded instruction includes a plurality of instruction bits. The queue is coupled to the decoder and adapted to store the first decoded instruction. The renamer has a first input port and a first and second output port. The renamer is coupled to the queue and adapted to receive the first decoded instruction at the input port, provide the first decoded instruction on the first output port, change at least one of the instruction bits to generate a second decoded instruction, and provide the second decoded instruction on the second output port. A method for expanding program instructions in a microprocessor having a renamer is provided. The renamer includes a first input port and first and second output ports. The method includes receiving a first decoded instruction in the first input port. The first decoded instruction includes a plurality of instruction bits. At least one of the instruction bits of the first instruction is changed to generate a second instruction. The first decoded instruction is provided on the first output port, and the second decoded instruction is provided on the second output port.
摘要翻译：微处理器包括解码器，队列和重命名器。解码器适于接收程序指令并对程序指令进行解码以提供第一解码指令。第一解码指令包括多个指令位。队列被耦合到解码器并适于存储第一解码指令。重命名器具有第一输入端口和第一和第二输出端口。所述重命名器耦合到所述队列并且适于在所述输入端口处接收所述第一解码指令，在所述第一输出端口上提供所述第一解码指令，改变所述指令位中的至少一个以生成第二解码指令，并且提供所述第二解码指令第二个输出端口的解码指令。提供了一种用于在具有重新映射器的微处理器中扩展程序指令的方法。重命名器包括第一输入端口和第一和第二输出端口。该方法包括在第一输入端口中接收第一解码指令。第一解码指令包括多个指令位。第一指令的至少一个指令位被改变以产生第二指令。第一解码指令被提供在第一输出端口上，第二解码指令被提供在第二输出端口上。

6. 发明授权

US6044456A Electronic system and method for maintaining synchronization of multiple front-end pipelines 失效
标题翻译：用于保持多个前端管道同步的电子系统和方法
公开(公告)号：US6044456A
公开(公告)日：2000-03-28
申请号：US002774
申请日：1998-01-05
申请人： Keshavram N. Murty , Nazar A. Zaidi , Darshana S. Shah , Tse-Yu Yeh
发明人： Keshavram N. Murty , Nazar A. Zaidi , Darshana S. Shah , Tse-Yu Yeh
IPC分类号： G06F9/38
CPC分类号： G06F9/3869
摘要： A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.
摘要翻译：描述了一种用于维持通过并行操作的多个前端管道传播的信息的同步的系统和方法。通常，这些多个前端管道响应于失速状态而变得异步，并且通过冲洗两个前端管道以及通过在不同的时间段内选择性地将这些前端管道从其失速状态中选择性地释放而重新建立同步。

7. 发明授权

US5961615A Method and apparatus for queuing data 失效
标题翻译：排队数据的方法和装置
公开(公告)号：US5961615A
公开(公告)日：1999-10-05
申请号：US2236
申请日：1997-12-31
申请人： Nazar A. Zaidi , Michael J. Morrison , Bharat Zaveri
发明人： Nazar A. Zaidi , Michael J. Morrison , Bharat Zaveri
IPC分类号： G06F5/06 , G06F9/38 , G06F13/38
CPC分类号： G06F9/3814 , G06F5/06 , G06F9/3802 , G06F9/383 , G06F9/3834 , G06F9/3842
摘要： A queue structure includes a plurality of entries, a plurality of ports coupled to the entries, a plurality of enable lines coupled to the entries and the ports, and control logic. Each enable line is adapted to enable a selected port to communicate with a selected entry. The control logic is adapted to enable at least two enable lines and allow at least one of the ports to communicate with at least two of the entries concurrently. A method for storing data in a queue is provided. The queue includes a plurality of entries, a plurality of ports coupled to the entries, and a plurality of enable lines coupled to the entries and the ports. Each enable line is adapted to enable a selected port to communicate with a selected entry. The method includes receiving a first instruction on one of the ports. A first enable line is enabled to allow the port to communicate with a first entry. The first instruction is stored in the first entry. A second enable line is enabled concurrent with enabling the first enable line to allow the port to communicate with a second entry. The first instruction is stored in the second entry.
摘要翻译：队列结构包括多个条目，耦合到条目的多个端口，耦合到条目和端口的多个使能线以及控制逻辑。每个使能线适于使所选择的端口与所选择的条目进行通信。所述控制逻辑适于使得至少两个使能线路能够允许所述端口中的至少一个同时与所述条件中的至少两个通信。提供了一种在队列中存储数据的方法。队列包括多个条目，耦合到条目的多个端口以及耦合到条目和端口的多个使能线。每个使能线适于使所选择的端口与所选择的条目进行通信。该方法包括在其中一个端口上接收第一指令。启用第一个启用行以允许端口与第一个条目进行通信。第一个指令存储在第一个条目中。启用第二个启用行，使第一个启用行允许端口与第二个条目进行通信。第一个指令存储在第二个条目中。

8. 发明授权

US07392369B2 Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check 失效
标题翻译：将建筑操作分解为投机和建筑微观操作，用于投机执行他人和违规检查
公开(公告)号：US07392369B2
公开(公告)日：2008-06-24
申请号：US11406879
申请日：2006-04-18
申请人： Jeffery J. Baxter , Gary N. Hammond , Nazar A. Zaidi
发明人： Jeffery J. Baxter , Gary N. Hammond , Nazar A. Zaidi
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3859
摘要： Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations which perform computations, or an architectural operations which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
摘要翻译：实施例包括各种方法，装置和系统，其中处理器包括乱序发布引擎和顺序执行流水线。对于一些实施例，问题引擎可能远离执行流水线，并且执行资源可能距离问题引擎很多时钟周期。问题引擎将操作分类为执行计算的推测操作或具有故障或引起异常的可能性的架构操作中的至少一个。潜在的除外操作可以分解成两个单独的微操作：推测微操作，其用于推测性地生成数据结果，以便可以推测地发布依赖于结果的操作，以及建筑微操作，其指示故障除外操作的条件。存储操作成为架构操作，并且可以保证所有以前的故障条件在发布存储之前进行评估。

9. 发明授权

US06237088B1 System and method for tracking in-flight instructions in a pipeline 失效
标题翻译：用于跟踪流水线中的飞行指令的系统和方法
公开(公告)号：US06237088B1
公开(公告)日：2001-05-22
申请号：US09089736
申请日：1998-06-03
申请人： Nazar A. Zaidi
发明人： Nazar A. Zaidi
IPC分类号： G06F942
CPC分类号： G06F9/3812
摘要： An apparatus, system and method are described for tracking in-flight line addresses. Such tracking enables a determination of a self-modifying code (SMC) conflict. In one embodiment, the apparatus comprises a line address buffer and companion logic. The line address buffer contains a first plurality of line addresses. Each line address is associated with a fetched instruction pointer. The comparison logic compares a second plurality of line addresses with an address of an instruction being executed in order to detect an event.
摘要翻译：描述了用于跟踪飞行中线路地址的装置，系统和方法。这种跟踪使得能够确定自修改代码（SMC）冲突。在一个实施例中，该装置包括行地址缓冲器和伴随逻辑。行地址缓冲器包含第一多行行地址。每个行地址与获取的指令指针相关联。比较逻辑将第二多个行地址与正在执行的指令的地址进行比较，以便检测事件。

10. 发明授权

US6055652A Multiple segment register use with different operand size 有权
公开(公告)号：US6055652A
公开(公告)日：2000-04-25
申请号：US314439
申请日：1999-05-19
申请人： Nazar A. Zaidi , Kenneth D. Shoemaker , Gary N. Hammond
发明人： Nazar A. Zaidi , Kenneth D. Shoemaker , Gary N. Hammond
IPC分类号： G06F12/14 , G06F11/16
CPC分类号： G06F12/1441
摘要： A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

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