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1. 发明申请

US20110145506A1 Replacing Cache Lines In A Cache Memory 有权
标题翻译：更换高速缓存内存中的高速缓存行
公开(公告)号：US20110145506A1
公开(公告)日：2011-06-16
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

2. 发明授权

US08990506B2 Replacing cache lines in a cache memory based at least in part on cache coherency state information 有权
标题翻译：至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
公开(公告)号：US08990506B2
公开(公告)日：2015-03-24
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

3. 发明授权

US09418011B2 Region based technique for accurately predicting memory accesses 有权
标题翻译：用于准确预测存储器访问的基于区域的技术
公开(公告)号：US09418011B2
公开(公告)日：2016-08-16
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

4. 发明申请

US20110320762A1 REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES 有权
标题翻译：准确预测存储器访问的基于区域的技术
公开(公告)号：US20110320762A1
公开(公告)日：2011-12-29
申请号：US12821935
申请日：2010-06-23
申请人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
发明人： Livio B. Soares , Naveen Cherukuri , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/10 , G06F12/1027 , G06F2212/6024
摘要： In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.
摘要翻译：在一个实施例中，本发明包括一个包括页面跟踪缓冲器（PTB）的处理器，该PTB包括多个条目以将地址存储到高速缓存页面并且存储签名以跟踪对高速缓存的每个高速缓存行的访问页面和PTB处理程序，PTB处理程序将条目加载到PTB中并更新签名。还描述和要求保护其他实施例。

5. 发明申请

US20140181477A1 Compressing Execution Cycles For Divergent Execution In A Single Instruction Multiple Data (SIMD) Processor 有权
标题翻译：在单指令多数据（SIMD）处理器中压缩执行循环
公开(公告)号：US20140181477A1
公开(公告)日：2014-06-26
申请号：US13724633
申请日：2012-12-21
申请人： Aniruddha S. Vaidya , Anahita Shayesteh , Dong Hyuk Woo , Saikat Saharoy , Mani Azimi
发明人： Aniruddha S. Vaidya , Anahita Shayesteh , Dong Hyuk Woo , Saikat Saharoy , Mani Azimi
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30058 , G06F9/30072 , G06F9/30181 , G06F9/3887
摘要： In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有向量执行单元的处理器，用于对具有多个单独数据元素的向量执行向量指令，其中向量指令具有第一宽度，并且向量执行单元具有较小宽度。所述处理器还包括耦合到所述向量执行单元的控制逻辑，以便当所述各个数据元素中的至少一些不被所述向量指令操作时，压缩执行所述向量指令时所消耗的执行周期数。描述和要求保护其他实施例。

6. 发明授权

US09424191B2 Scalable coherence for multi-core processors 有权
标题翻译：多核处理器的可扩展一致性
公开(公告)号：US09424191B2
公开(公告)日：2016-08-23
申请号：US13539044
申请日：2012-06-29
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/0831 , G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815 , Y02D10/13
摘要： An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
摘要翻译：一个方面的装置包括多个芯。多个核心被逻辑地分组成多个群集。集群共享基于映射的一致性目录与多个核心耦合，并且用于跟踪多个核心之间的数据共享。集群共享基于映射的一致性目录包括用于存储对应的地址对和集群标识符的标签阵列。每个地址都是识别数据。每个集群标识符用于标识其中一个集群。集群共享基于映射的一致性目录还包括一个集群共享映射数组来存储集群共享映射。每个集群共享映射对应于一对地址和集群标识符。每个集群共享映射是指示由由对应的集群标识符标识的集群内的相应地址所标识的数据的集群内共享。

7. 发明申请

US20140006714A1 SCALABLE COHERENCE FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的可缩放相关性
公开(公告)号：US20140006714A1
公开(公告)日：2014-01-02
申请号：US13539044
申请日：2012-06-29
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815 , Y02D10/13
摘要： An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
摘要翻译：一个方面的装置包括多个芯。多个核心被逻辑地分组成多个群集。集群共享基于映射的一致性目录与多个核心耦合，并且用于跟踪多个核心之间的数据共享。集群共享基于映射的一致性目录包括用于存储对应的地址对和集群标识符的标签阵列。每个地址都是识别数据。每个集群标识符用于标识其中一个集群。集群共享基于映射的一致性目录还包括一个集群共享映射数组来存储集群共享映射。每个集群共享映射对应于一对地址和集群标识符。每个集群共享映射是指示由由对应的集群标识符标识的集群内的相应地址所标识的数据的集群内共享。

8. 发明授权

US08683136B2 Apparatus and method for improving data prefetching efficiency using history based prefetching 有权
标题翻译：用于使用基于历史的预取来提高数据预取效率的装置和方法
公开(公告)号：US08683136B2
公开(公告)日：2014-03-25
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

9. 发明申请

US20120166733A1 APPARATUS AND METHOD FOR IMPROVING DATA PREFETCHING EFFICIENCY USING HISTORY BASED PREFETCHING 有权
标题翻译：使用基于历史的预编译改进数据预取效率的装置和方法
公开(公告)号：US20120166733A1
公开(公告)日：2012-06-28
申请号：US12976775
申请日：2010-12-22
申请人： Naveen Cherukuri , Mani Azimi
发明人： Naveen Cherukuri , Mani Azimi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

10. 发明申请

US20140376557A1 MODULAR DECOUPLED CROSSBAR FOR ON-CHIP ROUTER 有权
标题翻译：用于片上路由器的模块化解交叉
公开(公告)号：US20140376557A1
公开(公告)日：2014-12-25
申请号：US13994801
申请日：2012-02-09
申请人： Dongkonk Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
发明人： Dongkonk Park , Aniruddha Vaidya , Akhilesh Kumar , Mani Azimi
IPC分类号： H04L12/933
CPC分类号： H04L49/101 , G06F15/17381 , G06F15/7825 , H04L49/109 , H04L49/15 , Y02D10/12 , Y02D10/13
摘要： Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5×5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.
摘要翻译：布局感知的模块化去耦交叉开关和路由器，用于片上互连和相关的微架构和操作方法。公开了一种称为MoDe-X（模块化解耦交叉开关）的交叉开关和路由器架构，其支持用于2D网状互连的5端口路由，并且通过使用去耦的行和列子交叉模块与馈线布线和控制逻辑这可以在行和列子交叉杆模块上的端口之间进行路由。相应的MoDe-X路由器支持各种路由器输入和输出端口组合之间的5端口路由，与传统的5×5交叉开关设计和实现相比，可以减少路由器面积和功耗。 MoDe-X微架构可以配置为支持单端口和双端口注入配置。

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