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1. 发明授权

US06787858B2 Carrier injection protection structure 有权
标题翻译：载体注入保护结构
公开(公告)号：US06787858B2
公开(公告)日：2004-09-07
申请号：US10272336
申请日：2002-10-16
申请人： Moaniss Zitouni , Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice Parris
发明人： Moaniss Zitouni , Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice Parris
IPC分类号： H01L2994
CPC分类号： H01L27/0921 , H01L21/761 , H01L2924/0002 , H01L2924/00
摘要： A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.
摘要翻译：结构保护CMOS逻辑免受由功率器件的感应开关引起的衬底少数载流子注入。单个集成电路（IC）支持一个或多个功率MOSFET和一个或多个CMOS逻辑阵列。在功率MOSFET的漏极和CMOS逻辑阵列之间形成高度掺杂的环，以为注入的少数载流子提供低电阻的接地路径。在CMOS逻辑下是高掺杂掩埋层，以形成注入的少数载流子的高复合区域。一个或多个CMOS器件形成在掩埋层上方。衬底是电阻的，并且注入的电流被衰减。 CMOS器件休息的阱为注入的少数载流子形成低电阻接地层。

2. 发明授权

US07211477B2 High voltage field effect device and method 有权
公开(公告)号：US07211477B2
公开(公告)日：2007-05-01
申请号：US11124469
申请日：2005-05-06
申请人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
发明人： Edouard D. de Frésart , Richard J. De Souza , Xin Lin , Jennifer H. Morrison , Patrice M. Parris , Moaniss Zitouni
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/0847 , H01L29/7833 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

3. 发明申请

US20160049508A1 BIDIRECTIONAL TRENCH FET WITH GATE-BASED RESURF 有权
标题翻译：双向TRENCH FET与基于盖的RESURF
公开(公告)号：US20160049508A1
公开(公告)日：2016-02-18
申请号：US14926288
申请日：2015-10-29
申请人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Michael F. Petras , Ganming Qin , Evgueniy N. Stefanov , Dragan Zupac
发明人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Michael F. Petras , Ganming Qin , Evgueniy N. Stefanov , Dragan Zupac
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/063 , H01L29/086 , H01L29/0865 , H01L29/40 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/417 , H01L29/41741 , H01L29/423 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.
摘要翻译：一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

4. 发明申请

US20150372130A1 POWER DEVICE TERMINATION STRUCTURES AND METHODS 有权
标题翻译：电力设备终止结构和方法
公开(公告)号：US20150372130A1
公开(公告)日：2015-12-24
申请号：US14307678
申请日：2014-06-18
申请人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
发明人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/423 , G06F17/50 , H01L29/40
CPC分类号： H01L29/7813 , G06F17/5009 , G06F17/5072 , H01L29/063 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.
摘要翻译：本文公开了功率器件端接结构和方法。该结构包括沟槽栅极半导体器件。沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。内部晶体管包括具有平均内部区域间隔的多个内部沟槽。外部晶体管包括具有平均端接区域间隔的多个外部沟槽。平均端接区域间隔大于平均内部区域间隔，或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

5. 发明授权

US09419128B2 Bidirectional trench FET with gate-based resurf 有权
公开(公告)号：US09419128B2
公开(公告)日：2016-08-16
申请号：US14926288
申请日：2015-10-29
申请人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Michael F. Petras , Ganming Qin , Evgueniy N. Stefanov , Dragan Zupac
发明人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Michael F. Petras , Ganming Qin , Evgueniy N. Stefanov , Dragan Zupac
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L27/088 , H01L29/40 , H01L29/06 , H01L29/08 , H01L29/417
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/063 , H01L29/086 , H01L29/0865 , H01L29/40 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/417 , H01L29/41741 , H01L29/423 , H01L29/4236 , H01L29/66666 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

6. 发明授权

US09362394B2 Power device termination structures and methods 有权
标题翻译：功率器件端接结构和方法
公开(公告)号：US09362394B2
公开(公告)日：2016-06-07
申请号：US14307678
申请日：2014-06-18
申请人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
发明人： Moaniss Zitouni , Edouard D. de Frésart , Pon Sung Ku , Ganming Qin
IPC分类号： H01L29/78 , G06F17/50 , H01L29/66 , H01L29/06 , H01L29/40 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/7813 , G06F17/5009 , G06F17/5072 , H01L29/063 , H01L29/0696 , H01L29/0852 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/66734 , H01L29/7811
摘要： Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.
摘要翻译：本文公开了功率器件端接结构和方法。该结构包括沟槽栅极半导体器件。沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。内部晶体管包括具有平均内部区域间隔的多个内部沟槽。外部晶体管包括具有平均端接区域间隔的多个外部沟槽。平均端接区域间隔大于平均内部区域间隔，或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

7. 发明授权

US08502287B2 Semiconductor devices with enclosed void cavities 有权
标题翻译：具有封闭空隙的半导体器件
公开(公告)号：US08502287B2
公开(公告)日：2013-08-06
申请号：US12902805
申请日：2010-10-12
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.
摘要翻译：通过在栅极和漏极区域之间形成基本上空的空隙来提供具有非常低栅极 - 漏极电容Cgd的场效应器件和IC。对于垂直FETS，在半导体（SC）中蚀刻空腔并且设置有栅极电介质衬垫。沉积在空腔中的多晶硅栅极具有延伸到下面的SC的中心裂隙（空管）。这种裂缝用于蚀刻多晶硅下面的SC中的空隙。然后通过由沉积或氧化形成的介电塞而封闭裂缝，而不会明显地填充蚀刻的空隙。常规的工艺步骤用于在包含栅极的空腔周围提供源区和体区，并在体区下面提供漂移空间和漏区。栅极和漏极之间的蚀刻空隙提供比使用低k电介质可以实现的更低的Cgd和Ron * Qg。

8. 发明授权

US07510938B2 Semiconductor superjunction structure 有权
标题翻译：半导体超结构结构
公开(公告)号：US07510938B2
公开(公告)日：2009-03-31
申请号：US11510030
申请日：2006-08-25
申请人： Edouard D. de Frésart
发明人： Edouard D. de Frésart
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/165 , H01L29/205 , H01L29/267 , H01L29/66712 , H01L29/73 , H01L29/772 , H01L29/7848 , H01L29/861 , Y10S438/912
摘要： Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.
摘要翻译：半导体结构和方法被提供用于采用超结构结构（81）的半导体器件（54-11,54-12）。该方法包括：形成（52-6）第一导电类型的第一半导体材料（70）的第一间隔开的区域（70-1,70-2,70-3,70-4等），形成（52-9）与第一空间分开区域（70-1）交错的相反导电类型的第二半导体材料（74）的第二间隔开的区域（74-1,74-2,74-3等），70-2,70-3,70-4等），其间具有PN结，从而形成超结构结构，其中第二区具有比相同载流子类型的第一区更高的迁移率。提供与超结构结构（81）接触的其它区域（88）以引导其中的控制电流流动。在优选实施例中，第一材料（70）是松弛的SiGe，第二材料（74）是应变硅。

9. 发明申请

US20100084705A1 SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE AND METHODS FOR THE FABRICATION THEREOF 有权
标题翻译：具有降低的排气容量的半导体器件及其制造方法
公开(公告)号：US20100084705A1
公开(公告)日：2010-04-08
申请号：US12627739
申请日：2009-11-30
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
摘要翻译：提供了具有减小的栅极 - 漏极电容的半导体器件的制造方法的实施例。在一个实施例中，该方法包括以下步骤：利用蚀刻掩模蚀刻半导体衬底中的沟槽，加宽沟槽以限定部分地延伸到沟槽上的蚀刻掩模的悬垂区域，以及将栅电极材料沉积到沟槽中突出地区。栅极电极材料在填充沟槽之前在悬垂区域之间合并，以在沟槽内产生空隙。半导体衬底的一部分通过空隙去除以在沟槽附近形成空隙。

10. 发明申请

US20090286372A1 SUPERJUNCTION TRENCH DEVICE FORMATION METHODS 有权
标题翻译：超音速装置形成方法
公开(公告)号：US20090286372A1
公开(公告)日：2009-11-19
申请号：US12511849
申请日：2009-07-29
申请人： Edouard D. de Frésart , Robert W. Baird
发明人： Edouard D. de Frésart , Robert W. Baird
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconductor materials of different conductivity type and different mobilities so that the second semiconductor material has a higher mobility for the same carrier type than the first semiconductor material, and providing an overlying third semiconductor material in which a trench is formed with sidewalls having thereon a fourth semiconductor material that has a higher mobility than the third material, adapted to carry current between source regions, through the fourth semiconductor material in the trench and the second semiconductor material in the device drift space to the drain. In a further embodiment, the first and third semiconductor materials are relaxed materials and the second and fourth semiconductor materials are strained semiconductor materials.
摘要翻译：为半导体器件提供了形成半导体结构的方法，该半导体器件采用超结构结构和具有嵌入式控制栅极的上覆沟槽。一个实施例包括形成具有不同导电类型和不同迁移率的第一和第二半导体材料的交错的第一和第二间隔开的区域，使得第二半导体材料对于与第一半导体材料相同的载体类型具有较高的迁移率，并提供覆盖第三半导体材料，其中沟槽形成有侧壁，其上具有第四半导体材料，第四半导体材料具有比第三材料更高的迁移率，适于在源极区域之间通过沟槽中的第四半导体材料和第二半导体材料中的第二半导体材料器件漂移空间到漏极。在另一个实施例中，第一和第三半导体材料是松弛材料，第二和第四半导体材料是应变半导体材料。

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