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1. 发明授权

US06927602B2 Mixed-voltage CMOS I/O buffer with thin oxide device and dynamic n-well bias circuit 有权
标题翻译：具有薄氧化器件和动态n阱偏置电路的混合电压CMOS I / O缓冲器
公开(公告)号：US06927602B2
公开(公告)日：2005-08-09
申请号：US10626601
申请日：2003-07-25
申请人： Ming-Dou Ker , Chia-Sheng Tsai , Che-Hao Chuang
发明人： Ming-Dou Ker , Chia-Sheng Tsai , Che-Hao Chuang
IPC分类号： H03K17/0814 , H03K17/10 , H03K19/094
CPC分类号： H03K17/08142 , H03K17/102
摘要： A buffer circuit on a first chip coupled between a first circuit on the first chip and a second circuit on a second chip including a driver circuit comprising at least a first PMOS transistor and a second PMOS transistor, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than a power supply voltage of the buffer circuit appears at the node, and a gate-tracking circuit coupled to provide a first bias and a second bias to the gate of the first PMOS transistor depending on the signal appearing at the node.
摘要翻译：耦合在第一芯片上的第一电路和第二芯片上的第二电路之间的第一芯片上的缓冲电路，包括至少包括第一PMOS晶体管和第二PMOS晶体管的驱动器电路，第二芯片的源极和漏极之一 PMOS晶体管耦合到第一PMOS晶体管的衬底，其中当具有高于缓冲电路的电源电压的电压电平的第一信号出现在节点处时，第二PMOS晶体管截止，栅极跟踪电路耦合以根据出现在节点处的信号向第一PMOS晶体管的栅极提供第一偏置和第二偏压。

2. 发明申请

US20050017754A1 Mixed-voltage cmos I/O buffer with thin oxide device and dynamic n-well bias circuit 有权
标题翻译：具有薄氧化器件和动态n阱偏置电路的混合电压cmos I / O缓冲器
公开(公告)号：US20050017754A1
公开(公告)日：2005-01-27
申请号：US10626601
申请日：2003-07-25
申请人： Ming-Dou Ker , Chia-Sheng Tsai , Che-Hao Chuang
发明人： Ming-Dou Ker , Chia-Sheng Tsai , Che-Hao Chuang
IPC分类号： H03K17/0814 , H03K17/10 , H03K19/094
CPC分类号： H03K17/08142 , H03K17/102
摘要： A buffer circuit on a first chip coupled between a first circuit on the first chip and a second circuit on a second chip including a driver circuit comprising at least a first PMOS transistor and a second PMOS transistor, one of the source and drain of the second PMOS transistor being coupled to the substrate of the first PMOS transistor, wherein the second PMOS transistor is turned off when a first signal having a voltage level higher than a power supply voltage of the buffer circuit appears at the node, and a gate-tracking circuit coupled to provide a first bias and a second bias to the gate of the first PMOS transistor depending on the signal appearing at the node.
摘要翻译：耦合在第一芯片上的第一电路和第二芯片上的第二电路之间的第一芯片上的缓冲电路，包括至少包括第一PMOS晶体管和第二PMOS晶体管的驱动器电路，第二芯片的源极和漏极之一 PMOS晶体管耦合到第一PMOS晶体管的衬底，其中当具有高于缓冲电路的电源电压的电压电平的第一信号出现在节点处时，第二PMOS晶体管截止，栅极跟踪电路耦合以根据出现在节点处的信号向第一PMOS晶体管的栅极提供第一偏置和第二偏压。

3. 发明授权

US07145382B2 Charge pump circuit suitable for low-voltage process 有权
标题翻译：电荷泵电路适用于低压工艺
公开(公告)号：US07145382B2
公开(公告)日：2006-12-05
申请号：US10861359
申请日：2004-06-07
申请人： Ming-Dou Ker , Chia-Sheng Tsai
发明人： Ming-Dou Ker , Chia-Sheng Tsai
IPC分类号： G05F3/24
CPC分类号： H02M3/073 , H02M2003/075 , H02M2003/077
摘要： The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.
摘要翻译：本发明公开了一种适用于低电压工艺的电荷泵电路。电荷泵电路由彼此连接的电压放大电路的级构成，并且两个相邻级的电压放大电路的操作由两组相反的定时信号控制。电压放大电路的每一级具有根据输入到第一和第二电容器的定时信号和反相定时信号的耦合对第一互补MOS（CMOS）晶体管和第二CMOS晶体管切换。然后，两个二极管器件将电荷引导到下一级，并且输出高于集成电路电压源的电压。本发明具有高泵浦增益的优点，并且还可以解决低压工艺中栅氧化层的可靠性问题。

4. 发明申请

US20050146375A1 Charge pump circuit suitable for low-voltage process 有权
标题翻译：电荷泵电路适用于低压工艺
公开(公告)号：US20050146375A1
公开(公告)日：2005-07-07
申请号：US10861359
申请日：2004-06-07
申请人： Ming-Dou Ker , Chia-Sheng Tsai
发明人： Ming-Dou Ker , Chia-Sheng Tsai
IPC分类号： G05F3/02 , G11C16/06 , H02M3/07
CPC分类号： H02M3/073 , H02M2003/075 , H02M2003/077
摘要： The present invention discloses a charge pump circuit suitable for a low-voltage process. The charge pump circuit is composed of stages of the voltage amplifying circuits connected each other, and the operation of two adjacent stages of voltage amplifying circuit is controlled by two opposite set of the timing signals. Each stage of the voltage amplifying circuit has a coupled pair of a first complementary MOS (CMOS) transistor and a second CMOS transistor switching in accordance with a timing signal and an inverse timing signal inputted into the first and second capacitors. Then, two diode devices guide charges to next stage, and a voltage higher than the integrated circuit voltage source is outputted. The present invention has advantage of high pumping gain, and the reliability issue of the gate oxide layer in the low-voltage process can be also solved.
摘要翻译：本发明公开了一种适用于低电压工艺的电荷泵电路。电荷泵电路由彼此连接的电压放大电路的级构成，并且两个相邻级的电压放大电路的操作由两组相反的定时信号控制。电压放大电路的每一级具有根据输入到第一和第二电容器的定时信号和反相定时信号的耦合对第一互补MOS（CMOS）晶体管和第二CMOS晶体管切换。然后，两个二极管器件将电荷引导到下一级，并且输出高于集成电路电压源的电压。本发明具有高泵浦增益的优点，并且还可以解决低压工艺中栅氧化层的可靠性问题。

5. 发明申请

US20070174523A1 APPARATUS AND METHOD FOR GENERATING BITSTREAM OF S/PDIF DATA IN HDMI 有权
标题翻译：用于生成HDMI中S / PDIF数据的BITSTREAM的装置和方法
公开(公告)号：US20070174523A1
公开(公告)日：2007-07-26
申请号：US11306703
申请日：2006-01-09
申请人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
发明人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
IPC分类号： G06F13/38
CPC分类号： G06F13/4295
摘要： An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a current control word of a current data unit and a previous control word of a previous data unit; and a transmitter for generating the bitstream of the first digital interconnect format according to the sample words of the data units and the selected control words outputted from the decision unit.
摘要翻译：公开了一种用于再生S / PDIF数据的装置和方法。该装置包括用于缓冲数据单元的采样字的缓冲器; 决定单元，用于接收数据单元的控制字，并根据当前数据单元的当前控制字和先前数据单元的先前控制字输出所选择的控制字; 以及发送器，用于根据数据单元的采样字和从判定单元输出的所选择的控制字来产生第一数字互连格式的比特流。

6. 发明申请

US20070239438A1 Digital microphone system and method thereof 审中-公开
标题翻译：数字麦克风系统及其方法
公开(公告)号：US20070239438A1
公开(公告)日：2007-10-11
申请号：US11730939
申请日：2007-04-05
申请人： Tsung-Peng Chuang , Chia-Sheng Tsai
发明人： Tsung-Peng Chuang , Chia-Sheng Tsai
IPC分类号： G10L21/00
CPC分类号： G10L19/00 , H04R1/005
摘要： A digital microphone system and a method thereof are described. The digital microphone comprises a receiving unit, an amplifier, a modulator, an audio processing unit and a high definition audio link. After the receiving unit receives an analog audio signal, the analog audio signal is amplified by the amplifier. The analog audio signal is then converted into a first digital data by the modulator. The high definition audio link is set between the modulator and the audio processing unit for transmitting the first digital data. The audio processing unit comprises a digital filter for converting the first digital data into a second digital data. The audio processing unit and the digital filter are integrated and implemented by software.
摘要翻译：描述了数字麦克风系统及其方法。数字麦克风包括接收单元，放大器，调制器，音频处理单元和高清晰度音频链路。在接收单元接收模拟音频信号之后，模拟音频信号被放大器放大。然后，模拟音频信号由调制器转换成第一数字数据。高分辨率音频链路设置在调制器和音频处理单元之间，用于发送第一数字数据。音频处理单元包括用于将第一数字数据转换为第二数字数据的数字滤波器。音频处理单元和数字滤波器由软件集成和实现。

7. 发明授权

US07549000B2 Apparatus and method for generating bitstream of S/PDIF data in HDMI 有权
标题翻译：用于在HDMI中生成S / PDIF数据的比特流的装置和方法
公开(公告)号：US07549000B2
公开(公告)日：2009-06-16
申请号：US11306703
申请日：2006-01-09
申请人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
发明人： Tzuo-bo Lin , Hsu-Jung Tung , Sheng-Nan Chiou , Chia-Sheng Tsai
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/4295
摘要： An apparatus and method for regenerating S/PDIF data is disclosed. The apparatus includes a buffer for buffering sample words of the data units; a decision unit for receiving control words of the data units and outputting a selected control word according to a current control word of a current data unit and a previous control word of a previous data unit; and a transmitter for generating the bitstream of the first digital interconnect format according to the sample words of the data units and the selected control words outputted from the decision unit.
摘要翻译：公开了一种用于再生S / PDIF数据的装置和方法。该装置包括用于缓冲数据单元的采样字的缓冲器; 决定单元，用于接收数据单元的控制字，并根据当前数据单元的当前控制字和先前数据单元的先前控制字输出所选择的控制字; 以及发送器，用于根据数据单元的采样字和从判定单元输出的所选择的控制字来产生第一数字互连格式的比特流。

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