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1. 发明授权

US08836387B1 Methods and systems for reducing jitter 有权
标题翻译：减少抖动的方法和系统
公开(公告)号：US08836387B1
公开(公告)日：2014-09-16
申请号：US12984356
申请日：2011-01-04
申请人： Jin Xie , Bin Ni , Mats Oberg
发明人： Jin Xie , Bin Ni , Mats Oberg
IPC分类号： H03L7/06
CPC分类号： H03L7/093
摘要： Methods and systems for compensating reducing jitter produced by a phase-locked loop are disclosed. For example, in a particular embodiment, a phase-locked loop device for reducing jitter may include a voltage-control oscillator (VCO) signal configured to produce a VCO signal, phase-detection circuitry configured to compare an input signal and the VCO signal to produce a phase error signal, and slew-rate limiting circuitry configured to receive the phase error signal and apply a slew-rate limit process on the phase error signal to produce a modified error signal.
摘要翻译：公开了用于补偿由锁相环产生的抖动的方法和系统。例如，在特定实施例中，用于减少抖动的锁相环装置可以包括被配置为产生VCO信号的电压控制振荡器（VCO）信号，相位检测电路被配置为将输入信号和VCO信号进行比较产生相位误差信号和摆率限制电路，其配置为接收相位误差信号，并对相位误差信号施加转换速率限制处理以产生修正的误差信号。

2. 发明授权

US08660171B1 Method and apparatus for timing jitter measurement 失效
标题翻译：定时抖动测量的方法和装置
公开(公告)号：US08660171B1
公开(公告)日：2014-02-25
申请号：US12192877
申请日：2008-08-15
申请人： Mats Oberg , Jin Xie , Bin Ni
发明人： Mats Oberg , Jin Xie , Bin Ni
IPC分类号： H04B17/00
CPC分类号： H04L1/205 , G01R31/31709 , H04B17/364
摘要： A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.
摘要翻译：用于测量数字域中的定时抖动的定时抖动测量电路可以使用内插器组对来自媒体读取器的信号进行过采样，零交叉估计器估计内插器组的输出中的零交叉时刻和时间间隔分析器（TIA）来计算定时抖动，作为估计的过零点与时钟信号中的预期过零点的偏差。定时抖动测量电路可以集成到数字电路中，因为它避免使用模拟设备。因此，它可以简化芯片设计，降低功耗并节省空间。

3. 发明授权

US08630155B2 Method and apparatus for offset and gain correction 有权
标题翻译：用于偏移和增益校正的方法和装置
公开(公告)号：US08630155B2
公开(公告)日：2014-01-14
申请号：US13101439
申请日：2011-05-05
申请人： Jin Xie , Bin Ni , Mats Oberg
发明人： Jin Xie , Bin Ni , Mats Oberg
IPC分类号： G11B15/52
CPC分类号： G11B20/10222 , G11B20/10009 , G11B20/10046 , G11B20/10203 , G11B20/10314 , G11B20/10351 , G11B20/10509 , G11B20/18 , G11B2020/1062 , G11B2220/2537
摘要： Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.
摘要翻译：本公开的方面提供了一种信号处理电路，其对电信号中的突然轮廓变化具有快速响应时间。信号处理电路包括处理路径，其被配置为处理响应于在存储介质上读取数据而产生的电信号和前馈校正模块。前馈校正模块被配置为基于时间窗中的电信号检测轮廓变化，并且基于检测到的轮廓变化来校正时间窗中的电信号。

4. 发明授权

US08493826B1 Method and apparatus for recording 有权
标题翻译：记录方法和装置
公开(公告)号：US08493826B1
公开(公告)日：2013-07-23
申请号：US13164232
申请日：2011-06-20
申请人： Mats Oberg , Jin Xie , Bin Ni
发明人： Mats Oberg , Jin Xie , Bin Ni
IPC分类号： G11B5/09
CPC分类号： G11B7/0053 , G11B19/041 , G11B27/24
摘要： Aspects of the disclosure provide a method for signal processing. The method includes receiving a tracking signal corresponding to a recording track on a storage medium. The tracking signal is frequency modulated with encoded symbols. Further, the method includes phase-locking an internal signal to the tracking signal to cause a frequency of the internal signal to be locked at a center frequency of the tracking signal, detecting a drift between the internal signal and the encoded symbols, and phase-shifting the internal signal to compensate for the drift.
摘要翻译：本公开的方面提供了一种用于信号处理的方法。该方法包括在存储介质上接收对应于记录轨道的跟踪信号。跟踪信号用编码符号进行频率调制。此外，该方法包括将内部信号相位锁定到跟踪信号，以使内部信号的频率被锁定在跟踪信号的中心频率处，检测内部信号与编码符号之间的漂移，移动内部信号以补偿漂移。

5. 发明申请

US20110273974A1 METHOD AND APPARATUS FOR OFFSET AND GAIN CORRECTION 有权
标题翻译：用于偏移和增益校正的方法和装置
公开(公告)号：US20110273974A1
公开(公告)日：2011-11-10
申请号：US13101439
申请日：2011-05-05
申请人： Jin Xie , Bin Ni , Mats Oberg
发明人： Jin Xie , Bin Ni , Mats Oberg
IPC分类号： G11B20/10
CPC分类号： G11B20/10222 , G11B20/10009 , G11B20/10046 , G11B20/10203 , G11B20/10314 , G11B20/10351 , G11B20/10509 , G11B20/18 , G11B2020/1062 , G11B2220/2537
摘要： Aspects of the disclosure provide a signal processing circuit that has fast response time to sudden profile changes in an electrical signal. The signal processing circuit includes a processing path configured to process an electrical signal that is generated in response to reading data on a storage medium, and a feed-forward correction module. The feed-forward correction module is configured to detect a profile variation based the electrical signal in a time window, and correct the electrical signal in the time window based on the detected profile variation.
摘要翻译：本公开的方面提供了一种信号处理电路，其对电信号中的突然轮廓变化具有快速响应时间。信号处理电路包括处理路径，其被配置为处理响应于在存储介质上读取数据而产生的电信号和前馈校正模块。前馈校正模块被配置为基于时间窗中的电信号检测轮廓变化，并且基于检测到的轮廓变化来校正时间窗中的电信号。

6. 发明授权

US07961124B1 Timing loop based on analog to digital converter output and method of use 有权
标题翻译：基于模数转换器输出的定时回路和使用方法
公开(公告)号：US07961124B1
公开(公告)日：2011-06-14
申请号：US12418285
申请日：2009-04-03
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/10
CPC分类号： H03M1/1255 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2537
摘要： A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
摘要翻译：一种用于补偿模拟输入信号（如果存在）的不对称质量并且产生定时信号的装置和过程。然后将定时信号用于模数转换。

7. 发明授权

US07525460B1 Timing loop based on analog to digital converter output and method of use 有权
标题翻译：基于模数转换器输出的定时回路和使用方法
公开(公告)号：US07525460B1
公开(公告)日：2009-04-28
申请号：US11775757
申请日：2007-07-10
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
摘要翻译：一种用于补偿模拟输入信号（如果存在）的不对称质量并且产生定时信号的装置和过程。然后将定时信号用于模数转换。

8. 发明授权

US08957793B1 Limit equalizer output based timing loop 有权
标题翻译：限制基于均衡器输出的定时循环
公开(公告)号：US08957793B1
公开(公告)日：2015-02-17
申请号：US13608365
申请日：2012-09-10
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/48
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.
摘要翻译：本公开的方面提供了一种方法。该方法包括：基于时钟信号升压从模拟信号转换的数字信号的一部分频率分量，基于升压数字信号产生判定信号，基于升压的数字信号产生定时误差信号;以及判定信号，并对定时误差信号进行滤波，生成电压信号，控制压控振荡器产生时钟信号。

9. 发明授权

US08830808B1 Method and apparatus for zero offset and gain start 有权
标题翻译：用于零偏移和增益启动的方法和装置
公开(公告)号：US08830808B1
公开(公告)日：2014-09-09
申请号：US12856762
申请日：2010-08-16
申请人： Bin Ni , Zachary Keirn , Mats Oberg
发明人： Bin Ni , Zachary Keirn , Mats Oberg
IPC分类号： G11B7/00
CPC分类号： G11B20/10009
摘要： Aspects of the disclosure provide a signal processing circuit. The signal processing circuit includes a processing path and a zero-start module. The processing path is configured to process an electrical signal that is generated in response to reading data on a storage medium. The data includes at least a first field and a second field. The electrical signal has a first profile corresponding to the first field and has a second profile corresponding to the second field. The zero-start module is configured to detect a field change from the first field to the second field, and control the processing path to add a compensation as a function of a profile change from the first profile to the second profile to keep the processed electrical signal to have a predetermined profile in response to the detected field change.
摘要翻译：本公开的方面提供了一种信号处理电路。信号处理电路包括处理路径和零起动模块。处理路径被配置为处理响应于在存储介质上读取数据而产生的电信号。该数据至少包括第一场和第二场。电信号具有对应于第一场的第一轮廓，并且具有对应于第二场的第二轮廓。零启动模块被配置为检测从第一场到第二场的场变化，并且控制处理路径以将补偿作为从第一轮廓到第二轮廓的轮廓变化的函数来添加，以保持经处理的电信号响应于检测到的场变化而具有预定的轮廓。

10. 发明授权

US08274413B1 Limit equalizer output based timing loop 有权
标题翻译：限制基于均衡器输出的定时循环
公开(公告)号：US08274413B1
公开(公告)日：2012-09-25
申请号：US12877779
申请日：2010-09-08
申请人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
发明人： Jingfeng Liu , Mats Oberg , Zachary Keirn , Bin Ni
IPC分类号： H03M1/48
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10203 , G11B20/10222 , G11B20/10296 , G11B2220/2562 , H03M1/0836 , H03M1/12
摘要： A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
摘要翻译：用于产生用于驱动模数转换器（ADC）的通道时钟信号的定时回路包括：限幅器偏置回路，被配置为产生用于来自ADC的数字输出信号的不对称补偿信号，第一加法器被配置为不对称地补偿数字输出基于来自限幅偏置环路的不对称补偿信号的限幅均衡器，被配置为限制来自加法器的非对称补偿的数字输出信号的升压幅度的限幅器，被配置为基于不对称补偿的数字输出信号产生临时判定信号的限幅器来自限幅均衡器的相位检测器被配置为基于来自极限均衡器的非对称补偿数字输出信号和来自限幅器的临时判定信号产生定时误差信号; 并且第一滤波器被配置为基于来自相位检测器的时间误差信号产生用于驱动ADC的时钟信号。

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