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1. 发明授权

US06389381B1 Method and apparatus for calculating delay times in semiconductor circuit 失效
标题翻译：用于计算半导体电路中的延迟时间的方法和装置
公开(公告)号：US06389381B1
公开(公告)日：2002-05-14
申请号：US09037063
申请日：1998-03-09
申请人： Masahito Isoda , Takashi Yoneda , Rieko Suzuki
发明人： Masahito Isoda , Takashi Yoneda , Rieko Suzuki
IPC分类号： G06F9455
CPC分类号： G06F17/5022
摘要： A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.
摘要翻译：用于计算电路延迟时间的方法和装置有效地布置和存储数据以减少系统存储器要求，这允许没有大容量存储设备的计算机（诸如具有有限硬盘空间的传统个人计算机）用于测试初步设备设计，延迟时间比例系数值表示由电路元件的预定参考延迟时间彼此相关大的依赖因子的值确定的延迟时间的比率存储在系数表中。依赖因素包括工艺条件，使用中或工作温度以及第一和第二工作电源电压。

2. 发明授权

US5618744A Manufacturing method and apparatus of a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法和装置
公开(公告)号：US5618744A
公开(公告)日：1997-04-08
申请号：US124702
申请日：1993-09-22
申请人： Rieko Suzuki , Kiyoshi Saida , Kazushige Itazu , Eiji Fujine , Yoshihiro Kamiya , Yoshitaka Uchida , Takako Murakami , Teruhisa Tsuyuki , Kazunori Kawazoe , Takeshi Shimazaki , Yukimi Nishiwaki
发明人： Rieko Suzuki , Kiyoshi Saida , Kazushige Itazu , Eiji Fujine , Yoshihiro Kamiya , Yoshitaka Uchida , Takako Murakami , Teruhisa Tsuyuki , Kazunori Kawazoe , Takeshi Shimazaki , Yukimi Nishiwaki
IPC分类号： G06F17/50 , H01L27/118 , H01L21/70
CPC分类号： H01L27/118 , G06F17/5068
摘要： According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
摘要翻译：根据本发明，使用用于设计半导体集成电路的计算机辅助设计系统，其中，形成电路网的多个逻辑单元根据指定在多个逻辑单元和连接端子的布线长度。

3. 发明授权

US06035111A Manufacturing method and apparatus of a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法和装置
公开(公告)号：US06035111A
公开(公告)日：2000-03-07
申请号：US748534
申请日：1996-11-13
申请人： Rieko Suzuki , Kiyoshi Saida , Kazushige Itazu , Eiji Fujine , Yoshihiro Kamiya , Yoshitaka Uchida , Takako Murakami , Teruhisa Tsuyuki , Kazunori Kawazoe , Takeshi Shimazaki , Yukimi Nishiwaki
发明人： Rieko Suzuki , Kiyoshi Saida , Kazushige Itazu , Eiji Fujine , Yoshihiro Kamiya , Yoshitaka Uchida , Takako Murakami , Teruhisa Tsuyuki , Kazunori Kawazoe , Takeshi Shimazaki , Yukimi Nishiwaki
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： H01L27/118 , G06F17/5068
摘要： According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
摘要翻译：根据本发明，使用用于设计半导体集成电路的计算机辅助设计系统，其中，形成电路网的多个逻辑单元根据指定在多个逻辑单元和连接端子的布线长度。

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