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1. 发明申请

US20130153956A1 SILICON ON INSULATOR INTEGRATED HIGH-CURRENT N TYPE COMBINED SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘子集成高电流N型组合半导体器件的硅
公开(公告)号：US20130153956A1
公开(公告)日：2013-06-20
申请号：US13819286
申请日：2011-07-11
申请人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
发明人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L27/0705 , H01L29/66325 , H01L29/7394
摘要： A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. It is characterized in that the N type base region is wrapped in the N type buffer region, and the drain electrode metal on the P type drain region is connected with the base electrode metal on the N type base region by a metal layer. In this invention, the current density of the device has been obviously improved without increasing the device area and reducing other performances of the device.
摘要翻译：一种绝缘体上集成的大电流N型组合半导体器件，其可以提高电流密度，包括P型衬底和其上布置的掩埋氧化物层。分为区域I和区域II的P型外延层布置在掩埋氧化物层上。区域I包括N型漂移区，P型深阱，N型缓冲阱，P型漏极区，N型源区和P型体接触区; 在硅表面上设置场氧化物层和玛瑙氧化物层，并且在栅极氧化物层上设置多晶硅晶格。区域II包括N型三极管漂移区，P型深阱，N型三极管缓冲阱，P型发射区，N型基极区，N型源区和P型体接触区; 在硅表面上设置场氧化物层和栅极氧化物层，并且在栅极氧化物层上设置多晶硅晶格。其特征在于，N型基极区域被包裹在N型缓冲区域中，P型漏极区域上的漏极金属通过金属层与N型基极区域上的基极金属连接。在本发明中，器件的电流密度明显提高，而不增加器件面积并降低器件的其他性能。

2. 发明授权

US08754442B2 Silicon on insulator integrated high-current N type combined semiconductor device 有权
标题翻译：绝缘子上集成大电流N型组合半导体器件
公开(公告)号：US08754442B2
公开(公告)日：2014-06-17
申请号：US13819286
申请日：2011-07-11
申请人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
发明人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L27/0705 , H01L29/66325 , H01L29/7394
摘要： A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.
摘要翻译：一种绝缘体上的N型半导体器件，包括N型漂移区，P型深阱，N型缓冲阱，P型漏极区，N型源区和P型体接触区; 布置在硅表面上的场氧化物层和栅氧化层，以及布置在栅氧化层上的多晶硅晶格; N型三极管漂移区，P型深阱，N型三极管缓冲阱，P型发射区，N型基极区域，N型源极区域和P型体接触区域; 设置在硅表面上的场氧化物层和栅氧化层，以及布置在栅极氧化物层上的多晶硅晶格。

3. 发明授权

US08933534B2 Isolation structure of high-voltage driving circuit 有权
标题翻译：高压驱动电路的隔离结构
公开(公告)号：US08933534B2
公开(公告)日：2015-01-13
申请号：US14240287
申请日：2012-08-14
申请人： Longxing Shi , Qinsong Qian , Weifeng Sun , Jing Zhu , Xianguo Huang , Shengli Lu
发明人： Longxing Shi , Qinsong Qian , Weifeng Sun , Jing Zhu , Xianguo Huang , Shengli Lu
IPC分类号： H01L21/761 , H01L29/36 , H01L29/06 , H01L21/265 , H01L29/78 , H01L21/8234 , H01L29/08 , H01L29/10
CPC分类号： H01L29/0646 , H01L21/265 , H01L21/761 , H01L21/823481 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/7835
摘要： An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.
摘要翻译：高电压驱动电路的隔离结构包括P型衬底和P型外延层; 在P型外延层上布置有高电压区域，低电压区域和高低压端子区域; 在高低压区和低电压区之间设置第一P型结隔离区，高电压区与低压区之间设置高压绝缘栅场效应管; 高压绝缘栅场效应管的两侧和高压绝缘栅场效应管与高边区之间的隔离结构形成为第二P型结隔离区。

4. 发明申请

US20120326688A1 SWITCHING POWER SUPPLY WITH QUICK TRANSIENT RESPONSE 有权
标题翻译：快速切换电源切换
公开(公告)号：US20120326688A1
公开(公告)日：2012-12-27
申请号：US13582971
申请日：2010-10-25
申请人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
发明人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： G05F1/618
CPC分类号： H02M3/1588 , H02M2001/0025 , H02M2003/1566 , Y02B70/1466
摘要： A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller (117) and a control signal gate (116) is added to the original PWM control loop of the switching power supply. The hysteretic controller (117) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller (117) are in a low potential, and the control signal gate (116) selects output signals (Qp1, Qn1) from a PWM controller (101) as input signals of a gate signal drive circuit (106). If the fluctuation of the output voltage (Vout) of the switching power supply exceeds the setting range of the hysteretic voltage, an output terminal (SELp, SELn) of the hysteretic controller (117) outputs a high potential, and the control signal gate (116) selects output signals (Qp2, Qn2) of the hysteretic controller (117) as input signals of the gate signal drive circuit (106), so the operation of switching tubes (111, 112) at the power lever (102) of the switching power supply is controlled to stabilize the output voltage (Vout).
摘要翻译：提供了具有快速瞬态响应的开关电源。包括迟滞控制器（117）和控制信号门（116）的迟滞控制回路被添加到开关电源的原始PWM控制环路中。迟滞控制器（117）用于检测开关电源的输出电压（Vout），并将开关电源的输出电压（Vout）与参考电压（Vref）进行比较。当开关电源的负载电流（Iout）突然改变时，开关电源的输出电压（Vout）波动。如果开关电源的输出电压（Vout）处于滞后电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）为低电位，控制信号门（116）选择来自PWM控制器（101）的输出信号（Qp1，Qn1）作为门信号驱动电路（106）的输入信号。如果开关电源的输出电压（Vout）的波动超过迟滞电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）输出高电位，控制信号门极 116）选择滞后控制器（117）的输出信号（Qp2，Qn2）作为门信号驱动电路（106）的输入信号，从而切换管（111,112）在动力杆（102）控制开关电源以稳定输出电压（Vout）。

5. 发明申请

US20120256671A1 SWITCH LEVEL CIRCUIT WITH DEAD TIME SELF-ADAPTING CONTROL 失效
标题翻译：切换电平电路与死时间自适应控制
公开(公告)号：US20120256671A1
公开(公告)日：2012-10-11
申请号：US13515801
申请日：2010-10-26
申请人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
发明人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
IPC分类号： H03K3/017
CPC分类号： H02M3/1588 , H02M2001/0048 , H02M2001/385 , Y02B70/1466 , Y02B70/1491
摘要： A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time. The control module comprises a sampling circuit (16) for detecting the current dead time at the node (LX), an adjusting circuit (17) for buffering and converting the sampling voltage sampled by the sampling circuit (16), and a controlled delay unit (15) equipped with an external control input terminal, wherein the controlled delay unit (15) delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor (11) as a control signal. The switch level circuit (110) has simple structure, better performance and wide application range.
摘要翻译：一种具有死区时间自适应控制的开关电平电路（110），其通过改变高侧控制晶体管（10）和低侧同步（10）之间的死区时间而使得具有同步整流的开关电源转换器的开关损耗最小化整流晶体管（11）。开关电平电路（110）包括通过外部控制信号控制为接通和断开的高侧控制晶体管（10）和低侧同步整流晶体管（11），具有给定占空比的波形为在两个晶体管之间的节点（LX）处输出。开关电平电路（110）还包括用于调节死区时间的控制模块。控制模块包括用于检测节点（LX）上的当前死区时间的采样电路（16），用于缓冲和转换由采样电路（16）采样的采样电压的调节电路（17），以及受控延迟单元（15），其中所述受控延迟单元（15）延迟外部控制信号，并将延迟的信号作为控制信号输出到低侧同步整流晶体管（11）的受控端子。开关电平电路（110）结构简单，性能好，应用范围广。

6. 发明授权

US07557634B2 Low-power consumption high-voltage CMOS driving circuit 失效
标题翻译：低功耗高压CMOS驱动电路
公开(公告)号：US07557634B2
公开(公告)日：2009-07-07
申请号：US11596272
申请日：2004-10-20
申请人： Longxing Shi , Weifeng Sun , Haisong Li , Shengli Lu , Yangbo Yi
发明人： Longxing Shi , Weifeng Sun , Haisong Li , Shengli Lu , Yangbo Yi
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K5/1515 , H03K17/162 , H03K2217/0036
摘要： The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit. The input end of the first out buffer unit is connected with the output end of the level switch stage as the input end of the out buffer stage, and the output end of the final output buffer unit is connected with another input end of the high voltage output stage as the output end of the out buffer stage.
摘要翻译：低功耗CMOS高压驱动电路涉及一种用于输出驱动的高压驱动电路，并且在电平开关级的输出端与高电压输出级的输入端之间存在一个缓冲级，包括高压PMOS管和高压NMOS管。高压PMOS管的源极与电源连接，其栅电极与上电平缓冲器的输出端连接，作为电流输出缓冲器的输入端。高压NMOS管的源极放在地，其栅电极作为第3序列信号的接收端。高压PMOS管的漏极区域与高压NMOS管的漏极区域连接，并与低电平输出缓冲器单元的输入端连接，作为当前电平输出缓冲单元的输出端。第一输出缓冲单元的输入端与电平开关级的输出端连接，作为输出缓冲级的输入端，最终输出缓冲单元的输出端连接高电压的另一输入端输出级作为输出缓冲级的输出端。

7. 发明授权

US08723496B2 Switching power supply with quick transient response 有权
标题翻译：开关电源具有快速瞬态响应
公开(公告)号：US08723496B2
公开(公告)日：2014-05-13
申请号：US13582971
申请日：2010-10-25
申请人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
发明人： Weifeng Sun , Miao Yang , Youshan Jin , Sichao Liu , Shen Xu , Shengli Lu , Longxing Shi
IPC分类号： G05F1/00
CPC分类号： H02M3/1588 , H02M2001/0025 , H02M2003/1566 , Y02B70/1466
摘要： A switching power supply with a quick transient response is provided. A hysteretic control loop which comprises a hysteretic controller (117) and a control signal gate (116) is added to the original PWM control loop of the switching power supply. The hysteretic controller (117) is used to detect an output voltage (Vout) of the switching power supply and compare the output voltage (Vout) of the switching power supply with a reference voltage (Vref). When a load current (Iout) of the switching power supply is suddenly changed, the output voltage (Vout) of the switching power supply fluctuates. If the output voltage (Vout) of the switching power supply is in a setting range of the hysteretic voltage, output terminals (SELp, SELn) of the hysteretic controller (117) are in a low potential, and the control signal gate (116) selects output signals (Qp1, Qn1) from a PWM controller (101) as input signals of a gate signal drive circuit (106). If the fluctuation of the output voltage (Vout) of the switching power supply exceeds the setting range of the hysteretic voltage, an output terminal (SELp, SELn) of the hysteretic controller (117) outputs a high potential, and the control signal gate (116) selects output signals (Qp2, Qn2) of the hysteretic controller (117) as input signals of the gate signal drive circuit (106), so the operation of switching tubes (111, 112) at the power lever (102) of the switching power supply is controlled to stabilize the output voltage (Vout).
摘要翻译：提供了具有快速瞬态响应的开关电源。包括迟滞控制器（117）和控制信号门（116）的迟滞控制回路被添加到开关电源的原始PWM控制环路中。迟滞控制器（117）用于检测开关电源的输出电压（Vout），并将开关电源的输出电压（Vout）与参考电压（Vref）进行比较。当开关电源的负载电流（Iout）突然改变时，开关电源的输出电压（Vout）波动。如果开关电源的输出电压（Vout）处于滞后电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）为低电位，控制信号门（116）选择来自PWM控制器（101）的输出信号（Qp1，Qn1）作为门信号驱动电路（106）的输入信号。如果开关电源的输出电压（Vout）的波动超过迟滞电压的设定范围，则迟滞控制器（117）的输出端子（SELp，SELn）输出高电位，控制信号门极 116）选择滞后控制器（117）的输出信号（Qp2，Qn2）作为门信号驱动电路（106）的输入信号，从而切换管（111,112）在动力杆（102）控制开关电源以稳定输出电压（Vout）。

8. 发明授权

US08659345B2 Switch level circuit with dead time self-adapting control 失效
标题翻译：开关电平电路具有死区时间自适应控制
公开(公告)号：US08659345B2
公开(公告)日：2014-02-25
申请号：US13515801
申请日：2010-10-26
申请人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
发明人： Shen Xu , Weifeng Sun , Miao Yang , Sichao Liu , Youshan Jin , Shengli Lu , Longxing Shi
IPC分类号： H03K17/687
CPC分类号： H02M3/1588 , H02M2001/0048 , H02M2001/385 , Y02B70/1466 , Y02B70/1491
摘要： A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time. The control module comprises a sampling circuit (16) for detecting the current dead time at the node (LX), an adjusting circuit (17) for buffering and converting the sampling voltage sampled by the sampling circuit (16), and a controlled delay unit (15) equipped with an external control input terminal, wherein the controlled delay unit (15) delays an external control signal and outputs the delayed signal to a controlled terminal of the low-side synchronous rectifying transistor (11) as a control signal. The switch level circuit (110) has simple structure, better performance and wide application range.
摘要翻译：一种具有死区时间自适应控制的开关电平电路（110），其通过改变高侧控制晶体管（10）和低侧同步（10）之间的死区时间而使得具有同步整流的开关电源转换器的开关损耗最小化整流晶体管（11）。开关电平电路（110）包括通过外部控制信号控制为接通和断开的高侧控制晶体管（10）和低侧同步整流晶体管（11），具有给定占空比的波形为在两个晶体管之间的节点（LX）处输出。开关电平电路（110）还包括用于调节死区时间的控制模块。控制模块包括用于检测节点（LX）上的当前死区时间的采样电路（16），用于缓冲和转换由采样电路（16）采样的采样电压的调节电路（17），以及受控延迟单元（15），其中所述受控延迟单元（15）延迟外部控制信号，并将延迟的信号作为控制信号输出到低侧同步整流晶体管（11）的受控端子。开关电平电路（110）结构简单，性能好，应用范围广。

9. 发明申请

US20070205820A1 Low-Power Consumption High-Voltage Cmos Driving Circuit 失效
标题翻译：低功耗高压Cmos驱动电路
公开(公告)号：US20070205820A1
公开(公告)日：2007-09-06
申请号：US11596272
申请日：2004-10-20
申请人： Longxing Shi , Weifeng Sun , Haisong Li , Yangbo Yi
发明人： Longxing Shi , Weifeng Sun , Haisong Li , Yangbo Yi
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K5/1515 , H03K17/162 , H03K2217/0036
摘要： The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit. The input end of the first out buffer unit is connected with the output end of the level switch stage as the input end of the out buffer stage, and the output end of the final output buffer unit is connected with another input end of the high voltage output stage as the output end of the out buffer stage.
摘要翻译：低功耗CMOS高压驱动电路涉及一种用于输出驱动的高压驱动电路，并且在电平开关级的输出端与高电压输出级的输入端之间存在一个缓冲级，包括高压PMOS管和高压NMOS管。高压PMOS管的源极与电源连接，其栅电极与上电平缓冲器的输出端连接，作为电流输出缓冲器的输入端。高压NMOS管的源极放在地，其栅电极作为第3序列信号的接收端。高压PMOS管的漏极区域与高压NMOS管的漏极区域连接，并与低电平输出缓冲器单元的输入端连接，作为当前电平输出缓冲单元的输出端。第一输出缓冲单元的输入端与电平开关级的输出端连接，作为输出缓冲级的输入端，最终输出缓冲单元的输出端连接高电压的另一输入端输出级作为输出缓冲级的输出端。

10. 发明授权

US08232993B2 Systems and methods for graphical rendering 有权
标题翻译：图形渲染的系统和方法
公开(公告)号：US08232993B2
公开(公告)日：2012-07-31
申请号：US11680885
申请日：2007-03-01
申请人： Weifeng Sun , Amar Mukherjee
发明人： Weifeng Sun , Amar Mukherjee
IPC分类号： G06T15/00
CPC分类号： G06T15/50
摘要： A computer readable medium configured to approximate the integral of the product of a plurality of functions includes logic configured to factor the plurality of functions into a set of fixed functions and one varying function, logic configured to determine a first vector that represents the product of the fixed functions in the wavelet domain, logic configured to determine a second vector that represents the one varying function in the wavelet domain, and logic configured to determine an inner product of the first vector and the second vector.
摘要翻译：被配置为近似多个函数的乘积的积分的计算机可读介质包括被配置为将多个函数归因为一组固定函数和一个变化函数的逻辑，逻辑被配置为确定表示第小波域中的固定函数，被配置为确定表示小波域中的一个变化函数的第二向量的逻辑，以及被配置为确定第一向量和第二向量的内积的逻辑。

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