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1. 发明申请

US20100008460A1 Synchronous de-skew with programmable latency for multi-lane high speed serial interface 有权
标题翻译：具有多通道高速串行接口的可编程延迟的同步去偏移
公开(公告)号：US20100008460A1
公开(公告)日：2010-01-14
申请号：US12218375
申请日：2008-07-11
申请人： Liang- Zhang , Hui Wang , Yong Wang
发明人： Liang- Zhang , Hui Wang , Yong Wang
IPC分类号： H04L7/00
CPC分类号： H04L25/14
摘要： A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.
摘要翻译：提出了一种用于在多通道高速串行接口上执行时钟校准和去偏移的方法和系统。与单个位通道相关联的多个串行通道收发器中的每一个接收包括训练序列头部模式的第一数据帧。基于第一数据帧中的每一个，多个串行通道收发器对多个数据帧进行偏移，并产生多个事件信号。使用多个事件信号，具有第一相位的核心时钟被调整为与最慢位通道相位对准。

2. 发明授权

US08073090B2 Synchronous de-skew with programmable latency for multi-lane high speed serial interface 有权
标题翻译：具有多通道高速串行接口的可编程延迟的同步去偏移
公开(公告)号：US08073090B2
公开(公告)日：2011-12-06
申请号：US12218375
申请日：2008-07-11
申请人： Liang Zhang , Hui Wang , Yong Wang
发明人： Liang Zhang , Hui Wang , Yong Wang
IPC分类号： H04L7/04
CPC分类号： H04L25/14
摘要： A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.
摘要翻译：提出了一种用于在多通道高速串行接口上执行时钟校准和去偏移的方法和系统。与单个位通道相关联的多个串行通道收发器中的每一个接收包括训练序列头部模式的第一数据帧。基于第一数据帧中的每一个，多个串行通道收发器对多个数据帧进行偏移，并产生多个事件信号。使用多个事件信号，具有第一相位的核心时钟被调整为与最慢位通道相位对准。

3. 发明授权

US08138845B1 Method and apparatus for auto-frequency calibration for multi-band VCO 有权
标题翻译：用于多频带VCO的自动频率校准的方法和装置
公开(公告)号：US08138845B1
公开(公告)日：2012-03-20
申请号：US12561039
申请日：2009-09-16
申请人： Yu Zhang , Liang Zhang , Yong Wang , Xin Liu
发明人： Yu Zhang , Liang Zhang , Yong Wang , Xin Liu
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1265 , H03B2200/0048 , H03B2200/005 , H03J2200/10
摘要： A method and apparatus for auto-frequency calibration for multi-band VCO have been disclosed where a VCO is first adjusted to a major frequency band and then adjusted to a sub-band within the major frequency band.
摘要翻译：已经公开了一种用于多频带VCO的自动频率校准的方法和装置，其中VCO首先被调整到主频带，然后调整到主频带内的子频带。

4. 发明授权

US07692499B2 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering 有权
标题翻译：使用自适应滤波的数字补偿高度稳定的保持时钟生成技术
公开(公告)号：US07692499B2
公开(公告)日：2010-04-06
申请号：US12006368
申请日：2007-12-31
申请人： Xin Liu , Liang Zhang , Yong Wang
发明人： Xin Liu , Liang Zhang , Yong Wang
IPC分类号： H03L7/093 , H03L7/087 , H03L1/00
CPC分类号： H03L7/093 , H03L1/02 , H03L7/099 , H03L7/0996 , H03L7/235
摘要： A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.
摘要翻译：提出了利用集成电路和外部OCXO产生高度稳定的保持时钟的系统和方法。集成电路包括输入参考时钟接收器，相位和频率检测器，其在输入参考时钟信号和反馈时钟信号之间产生误差信号，存储模型参数以预测OCXO的频率变化的数据存储块，适应性滤波模块，其包括数字环路滤波器和用于更新模型参数并且基于该模型预测频率变化的算法，使得系统能够在正常或保持模式下操作的开关，数字控制振荡器和反馈分频器的开关。

5. 发明授权

US08548773B2 High speed chip screening method using delay locked loop 有权
标题翻译：使用延迟锁定环的高速芯片筛选方法
公开(公告)号：US08548773B2
公开(公告)日：2013-10-01
申请号：US12607576
申请日：2009-10-28
申请人： Junqiang Shang , Liang Zhang , Yong Wang , Xin Liu
发明人： Junqiang Shang , Liang Zhang , Yong Wang , Xin Liu
IPC分类号： G06F11/30 , H03L7/06
CPC分类号： G01R31/31718 , G01R31/31725
摘要： A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed.
摘要翻译：用于测量芯片的最大速度的电压控制延迟线（VCDL）包括被配置为接收参考时钟信号的第一输入，被配置为输出输出时钟信号的第一输出和被配置为接收相位误差信号的第二输入表示参考和输出时钟信号之间的相位延迟。寄存器将由VCDL施加的延迟码存储到参考时钟信号以延迟参考时钟信号以产生输出时钟信号。根据相位误差信号调整延迟码，直到相位延迟等于预定值。当相位延迟等于预定值时，第二输出耦合到从寄存器读取延迟码并将延迟代码输出到自动测试设备的接口。输出的延迟代码对应于最大芯片速度。

6. 发明授权

US07995698B2 Method for binary clock and data recovery for fast acquisition and small tracking error 有权
标题翻译：用于快速采集和小跟踪误差的二进制时钟和数据恢复方法
公开(公告)号：US07995698B2
公开(公告)日：2011-08-09
申请号：US11906004
申请日：2007-09-28
申请人： Xin Liu , Liang Zhang , Yong Wang
发明人： Xin Liu , Liang Zhang , Yong Wang
IPC分类号： H03L7/08 , H03D3/24
CPC分类号： H04L7/033 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/093 , H03L2207/50 , H04L7/0008 , H04L7/0337 , H04L7/10
摘要： A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.
摘要翻译：提出了一种用于高速串行收发器应用中的时钟和数据恢复的新型方法和系统，其允许快速位锁定和小数据跟踪误差。时钟和数据恢复方法利用可变带宽环路滤波器来产生由相位内插器用于产生与输入数字数据流相同频率和相位的时钟信号的相位调整信号。可以将环路滤波器带宽调整为与多个时钟和数据恢复操作模式相对应。特别地，取决于恢复的时钟信号和输入的数字数据流之间的相位差是否高于或低于编程的阈值，滤波器带宽可以被设置为高或低的值。

7. 发明申请

US20090167443A1 Digitally compensated highly stable holdover clock generation techniques using adaptive filtering 有权
标题翻译：使用自适应滤波的数字补偿高度稳定的保持时钟生成技术
公开(公告)号：US20090167443A1
公开(公告)日：2009-07-02
申请号：US12006368
申请日：2007-12-31
申请人： Xin Liu , Liang Zhang , Yong Wang
发明人： Xin Liu , Liang Zhang , Yong Wang
IPC分类号： H03L7/099 , H03L7/00 , H03L7/085
CPC分类号： H03L7/093 , H03L1/02 , H03L7/099 , H03L7/0996 , H03L7/235
摘要： A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.
摘要翻译：提出了利用集成电路和外部OCXO产生高度稳定的保持时钟的系统和方法。集成电路包括输入参考时钟接收器，相位和频率检测器，其在输入参考时钟信号和反馈时钟信号之间产生误差信号，存储模型参数以预测OCXO的频率变化的数据存储块，自适应滤波模块，其包括数字环路滤波器和用于更新模型参数并且基于该模型预测频率变化的算法，使得系统能够在正常或保持模式下操作的开关，数字控制振荡器和反馈分频器的开关。

8. 发明申请

US20090086872A1 Method for binary clock and data recovery for fast acquisition and small tracking error 有权
标题翻译：用于快速采集和小跟踪误差的二进制时钟和数据恢复方法
公开(公告)号：US20090086872A1
公开(公告)日：2009-04-02
申请号：US11906004
申请日：2007-09-28
申请人： Xin Liu , Liang Zhang , Yong Wang
发明人： Xin Liu , Liang Zhang , Yong Wang
IPC分类号： H04L7/00 , H04L25/00
CPC分类号： H04L7/033 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/093 , H03L2207/50 , H04L7/0008 , H04L7/0337 , H04L7/10
摘要： A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value.
摘要翻译：提出了一种用于高速串行收发器应用中的时钟和数据恢复的新型方法和系统，其允许快速位锁定和小数据跟踪误差。时钟和数据恢复方法利用可变带宽环路滤波器来产生由相位内插器用于产生与输入数字数据流相同频率和相位的时钟信号的相位调整信号。可以将环路滤波器带宽调整为与多个时钟和数据恢复操作模式相对应。特别地，取决于恢复的时钟信号和输入的数字数据流之间的相位差是否高于或低于编程的阈值，滤波器带宽可以被设置为高或低的值。

9. 发明授权

US08093957B1 Method and apparatus for frequency compensation for multi-band VCO 有权
标题翻译：用于多频带VCO频率补偿的方法和装置
公开(公告)号：US08093957B1
公开(公告)日：2012-01-10
申请号：US12561166
申请日：2009-09-16
申请人： Liang Zhang , Yong Wang , Xin Liu , Yu Zhang
发明人： Liang Zhang , Yong Wang , Xin Liu , Yu Zhang
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1265 , H03B5/1293
摘要： A method and apparatus for frequency compensation for multi-band VCO have been disclosed where a VCO tank loading capacitance is adjusted slowly to allow VCO operation in a linear range.
摘要翻译：已经公开了用于多频带VCO的频率补偿的方法和装置，其中VCO容器负载电容被缓慢调节以允许VCO在线性范围内操作。

10. 发明授权

US07590025B2 Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design 有权
标题翻译：在源同步DDR2接口设计中清洁DQS信号产生的系统和方法
公开(公告)号：US07590025B2
公开(公告)日：2009-09-15
申请号：US12004177
申请日：2007-12-19
申请人： Yong Wang , Liang Zhang , Xin Liu
发明人： Yong Wang , Liang Zhang , Xin Liu
IPC分类号： G11C8/18
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.
摘要翻译：提出了一种用于生成信号以同步存储器接口设计中的DQ数据传输的方法和电路。所提出的方法包括在数据传输脉冲串同步信号边沿转换之后接收具有在前后周期之前的前导码周期的选通信号，确定选通信号前导码周期的定时位置，确定选通信号后同步周期的定时位置并且产生干净的选通信号，其在选通信号前导码开始之后并且在选通信号后同步码结束之后，基于选通信号前导码和后置信号的相应确定的定时位置跟踪选通信号的数据传输脉冲串同步边沿转变，时间段以这种方式，DQ数据传输可以根据突发同步信号边沿转变和在前导码和后导码周期期间由选通信号电平抖动引起的错误来同步。

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