会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Memory having charge-carrying floating gate memory cells with
time/voltage dependent refresh
    • 具有带时间/电压相关刷新的带电荷的浮动栅极存储单元的存储器
    • US5818762A
    • 1998-10-06
    • US680699
    • 1996-07-17
    • Koichi MaariAkira Tanaka
    • Koichi MaariAkira Tanaka
    • G11C17/00G11C11/56G11C16/02G11C16/10G11C16/34G11C11/34
    • G11C16/3431G11C11/5621G11C11/5628G11C16/10G11C16/3418G11C5/145
    • A non-volatile memory device provided with a memory cell having a charge storage layer with a threshold voltage which changes in accordance with an amount of charge stored wherein one value from a plurality of possibles values is written into the memory cell, comprising an auxiliary internal power source; a means for adjusting an amount of charges stored by the charge storage layer in accordance with a state of application of the voltage; a time counting means for counting a time elapsed from when a final write operation is carried out with respect to the memory cell; and a refreshing means for comparing the time counted by the counting means and a preliminarily set charge holding time limit, supplying the voltage of the auxiliary internal power source to the memory cell when the counted time reaches the charge holding time limit, and performing a repeat write operation.
    • 一种非易失性存储器件,其具有具有电荷存储层的存储单元,所述电荷存储层具有阈值电压,所述阈值电压根据存储的电荷量而变化,其中来自多个可能值的一个值被写入所述存储单元,包括辅助内部 能量源; 用于根据电压的施加状态调整由电荷存储层存储的电荷量的装置; 时间计数装置,用于计数从对存储单元执行最终写入操作所经过的时间; 以及刷新装置,用于比较由计数装置计数的时间和预先设定的电荷保持时间限制,当计数时间达到电荷保持时间限制时,将辅助内部电源的电压提供给存储单元,并且执行重复 写操作。
    • 2. 发明授权
    • Method of manufacturing contact programmable ROM
    • 制造接触可编程ROM的方法
    • US06274438B1
    • 2001-08-14
    • US09295571
    • 1999-04-21
    • Koichi Maari
    • Koichi Maari
    • H01L218246
    • H01L27/11226H01L27/112
    • This invention provides contact programmable ROM which shortens TAT. The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor substrate, the first interlayer insulating layer 20 is formed on the whole surface, the first opening 21 is formed on the first interlayer insulating layer 20 above one source/drain region 15A of each memory cell, metal interconnect material 22 is filled in the first opening 21 to from a contact hole, and the second interlayer insulating layer 23 is formed over the metal interconnect material 22 and first interlayer insulating layer 20, and (b) a step in which the second opening 24 is formed on the second interlayer insulating layer 23 above the contact hole of specified memory cells, and interconnecting layer 25 is connected electrically to the contact hole is formed over the second interlayer insulating layer 23.
    • 本发明提供了缩短TAT的接触可编程ROM。制造过程包括两个步骤:(a)在半导体衬底上形成具有栅极区14和源极/漏极区15A和15B的多个存储单元的步骤, 第一层间绝缘层20形成在整个表面上,第一开口21形成在每个存储单元的一个源极/漏极区域15A之上的第一层间绝缘层20上方,金属互连材料22填充在第一开口21中以从 接触孔和第二层间绝缘层23形成在金属互连材料22和第一层间绝缘层20上,以及(b)第二开口24形成在触点上方的第二层间绝缘层23上的步骤 指定的存储单元的孔,并且互连层25电连接到形成在第二层间绝缘层23上的接触孔。
    • 3. 发明授权
    • Contact programmable ROM and method of manufacturing the same
    • 接触可编程ROM及其制造方法
    • US5925917A
    • 1999-07-20
    • US926713
    • 1997-09-10
    • Koichi Maari
    • Koichi Maari
    • H01L27/112H01L21/8246H01L29/76H01L29/94
    • H01L27/11226H01L27/112
    • This invention provides contact programmable ROM which shortens TAT.The manufacturing process comprises two steps of: (a) a step in which a plurality of memory cells having gate region 14 and source/drain regions 15A and 15B is formed on a semiconductor substrate, the first interlayer insulating layer 20 is formed on the whole surface, the first opening 21 is formed on the first interlayer insulating layer 20 above one source/drain region 15A of each memory cell, metal interconnect material 22 is filled in the first opening 21 to from a contact hole, and the second interlayer insulating layer 23 is formed over the metal interconnect material 22 and first interlayer insulating layer 20, and (b) a step in which the second opening 24 is formed on the second interlayer insulating layer 23 above the contact hole of specified memory cells, and interconnecting layer 25 is connected electrically to the contact hole is formed over the second interlayer insulating layer 23.
    • 本发明提供可缩短TAT的接触可编程ROM。 制造工艺包括以下两个步骤:(a)在半导体衬底上形成具有栅极区域14和源极/漏极区域15A和15B的多个存储单元的步骤,整体上形成第一层间绝缘层20 表面,第一开口21形成在每个存储单元的一个源极/漏极区域15A之上的第一层间绝缘层20上方,金属互连材料22从接触孔填充在第一开口21中,并且第二层间绝缘层 23形成在金属互连材料22和第一层间绝缘层20上,以及(b)第二开口24形成在指定存储单元的接触孔上方的第二层间绝缘层23上的步骤,以及互连层25 与第二层间绝缘层23形成在电接触孔上的电连接。
    • 6. 发明授权
    • Method of making a semiconductor device
    • 制造半导体器件的方法
    • US5510283A
    • 1996-04-23
    • US327718
    • 1994-10-24
    • Koichi Maari
    • Koichi Maari
    • H01L21/76H01L21/8247H01L27/115H01L29/788H01L29/792
    • H01L27/11521
    • A semiconductor device includes a semiconductor substrate, element isolation films, channel stop diffusion layers, and elements formed on the semiconductor substrate in spaced-apart relation from each other by means of the element isolation films. The element has a floating gate. The element isolation film has such a film thickness of that the conducting type of a portion of the semiconductor substrate under the element isolation film, which is disposed at a position where a control gate is formed on the upper surface of the element isolation film by way of the floating gate, is not inverted, and that the conducting type of a portion of the semiconductor substrate under the element isolation film, which is disposed at a position where the control gate is directly formed on the upper surface of the element isolation film, is inverted. With this arrangement, the elements are separated from each other by each element isolation film having a thinner thickness of .
    • 半导体器件包括半导体衬底,元件隔离膜,沟道阻挡扩散层以及通过元件隔离膜彼此隔开形成在半导体衬底上的元件。 该元件有一个浮动门。 元件隔离膜具有这样的膜厚度:在元件隔离膜下方的半导体衬底的一部分的导电类型被设置在元件隔离件的上表面上形成控制栅极的位置 通过浮动栅极的膜不被反转,并且元件隔离膜下的半导体衬底的部分的导电类型被设置在控制栅极直接形成在元件的上表面上的位置 隔离膜,倒置。 通过这种布置,元件通过具有较薄厚度的每个元件隔离膜彼此分离。
    • 7. 发明授权
    • Method of controlling digital content distribution, a method of reproducing digital content, and an apparatus using the same
    • 控制数字内容分发的方法,再现数字内容的方法以及使用该方法的装置
    • US07636691B2
    • 2009-12-22
    • US10690911
    • 2003-10-22
    • Koichi Maari
    • Koichi Maari
    • G06F21/00
    • G11B20/00086G06F21/10G06F2221/0797G06F2221/2101G06F2221/2153G06Q20/1235G06Q20/3674G06Q20/382G06Q20/3829G11B20/00144G11B20/00152G11B20/00181G11B20/0021G11B20/00224G11B20/0071H04L63/0428H04L63/0823Y10S707/99939
    • A digital content distribution control method, a digital content reproducing method, and a digital content reproducing apparatus. The digital content distributing side manipulates digital content by encrypting and compressing the same, transmits the manipulated digital content, an encrypted content key, and encrypted billing information to the other party of communication, and distributes to digital content proprietors the digital content usage fees collected based on digital content usage information received from the other party. On the other hand, the digital content reproducing side decrypts, in a single portable terminal, the manipulated digital content by the digital key and decompresses the decrypted digital content for reproduction. At the same time, the reproducing side decrements the billing information according to the use of the content and generates content usage information to be transmitted to the content distributing side. The digital content reproducing apparatus associated with the present invention is made portable to solve the above-mentioned problems.
    • 数字内容分发控制方法,数字内容再现方法和数字内容再现装置。 数字内容发布侧通过加密和压缩数字内容来操纵数字内容,将操作的数字内容,加密的内容密钥和加密的计费信息发送到另一方的通信,并向数字内容所有者分发基于收集的数字内容使用费 关于从另一方收到的数字内容使用信息。 另一方面,数字内容再现侧在单个便携式终端中通过数字密钥解密被处理的数字内容,并解密解密的数字内容以进行再现。 同时,再现侧根据内容的使用来减少记帐信息,并生成要发送到内容分发侧的内容使用信息。 与本发明相关联的数字内容再现装置是便携式的,以解决上述问题。
    • 10. 发明授权
    • Semiconductor device and method of forming the same
    • 半导体器件及其形成方法
    • US5545907A
    • 1996-08-13
    • US435653
    • 1995-05-05
    • Koichi Maari
    • Koichi Maari
    • H01L21/76H01L21/8247H01L27/115H01L29/788H01L29/792
    • H01L27/11521
    • A semiconductor device includes a semiconductor substrate, element isolation films, channel stop diffusion layers, and elements formed on the semiconductor substrate in spaced-apart relation from each other by means of the element isolation films. The element has a floating gate. The element isolation film has such a film thickness of that the conducting type of a portion of the semiconductor substrate under the element isolation film, which is disposed at a position where a control gate is formed on the upper surface of the element isolation film by way of the floating gate, is not inverted, and that the conducting type of a portion of the semiconductor substrate under the element isolation film, which is disposed at a position where the control gate is directly formed on the upper surface of the element isolation film, is inverted. With this arrangement, the elements are separated from each other by each element isolation film having a thinner thickness of .
    • 半导体器件包括半导体衬底,元件隔离膜,沟道阻挡扩散层以及通过元件隔离膜彼此隔开形成在半导体衬底上的元件。 该元件有一个浮动门。 元件隔离膜具有这样的膜厚度:在元件隔离膜下方的半导体衬底的一部分的导电类型被设置在元件隔离件的上表面上形成控制栅极的位置 通过浮动栅极的膜不被反转,并且元件隔离膜下的半导体衬底的部分的导电类型被设置在控制栅极直接形成在元件的上表面上的位置 隔离膜,倒置。 通过这种布置,元件通过具有较薄厚度的每个元件隔离膜彼此分离。