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1. 发明公开

US20230307387A1 MEMORY DEVICE 审中-公开
公开(公告)号：US20230307387A1
公开(公告)日：2023-09-28
申请号：US17822248
申请日：2022-08-25
申请人： Kioxia Corporation
发明人： Ayako KAWANISHI , Shinya ARAI
IPC分类号： H01L23/60 , H01L25/065 , H01L25/18 , H01L23/00
CPC分类号： H01L23/60 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511 , H01L2924/30205
摘要： A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.

2. 发明申请

US20230090711A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20230090711A1
公开(公告)日：2023-03-23
申请号：US17654440
申请日：2022-03-11
申请人： Kioxia Corporation
发明人： Ayako KAWANISHI , Kanako SHIGA , Takeo MORI
IPC分类号： H01L23/535 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device incudes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked one by one; and a contact that extends in the stacked body in the stacking direction, and is connected to a structure arranged on in the stacked body or below the stacked body. The contact includes: a second conductive layer that extends in the stacked body LM in the stacking direction, and serves as a core of the contact; and a second insulating layer that covers a sidewall of the second conductive layer, and serves as a liner of the contact. At least at a point close to the structure, when viewed in a cross section taken in a direction intersecting the stacking direction, a variation, in a circumferential direction of the contact, of a first distance from a center point of the second conductive layer to an outer edge of the second insulating layer is larger than a variation, in the circumferential direction of the contact, of a second distance from the center point to an outer edge of the second conductive layer.

3. 发明公开

US20240304576A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240304576A1
公开(公告)日：2024-09-12
申请号：US18586366
申请日：2024-02-23
申请人： Kioxia Corporation
发明人： Yuya KIYOMURA , Ayako KAWANISHI , Yuta TAGUCHI , Ayumi WATARAI , Ippei KUME
IPC分类号： H01L23/00 , H01L25/18 , H10B80/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/08 , H01L25/18 , H10B80/00 , H01L2224/03848 , H01L2224/05009 , H01L2224/05017 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05087 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05557 , H01L2224/05558 , H01L2224/05647 , H01L2224/08145 , H01L2924/1438
摘要： A memory device includes a first chip including a first electrode and a second chip including a second electrode. The first electrode includes a first conductive film having a first surface in contact with the second electrode at a boundary region of the first and second electrodes, a second surface spaced apart from the boundary region, and a third surface between the first surface and the second surface, and having a first portion on the first surface side and a second portion on the second surface side, and includes a second conductive film covering the second surface and the third surface of the first conductive film. A (111) orientation ratio of copper contained in the first portion is higher than a (111) orientation ratio of copper contained in the second portion.

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