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1. 发明授权

US08218374B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US08218374B2
公开(公告)日：2012-07-10
申请号：US12981163
申请日：2010-12-29
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

2. 发明授权

US08144513B2 Non-volatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08144513B2
公开(公告)日：2012-03-27
申请号：US12960882
申请日：2010-12-06
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

3. 发明申请

US20110075488A1 Non-Volatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110075488A1
公开(公告)日：2011-03-31
申请号：US12960882
申请日：2010-12-06
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

4. 发明授权

US07224621B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US07224621B2
公开(公告)日：2007-05-29
申请号：US11515005
申请日：2006-09-05
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

5. 发明申请

US20070016738A1 Nonvolatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20070016738A1
公开(公告)日：2007-01-18
申请号：US11530551
申请日：2006-09-11
申请人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Toshihiko Himeno , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00 , G06F9/00 , G06F15/177 , G11C16/06 , G11C11/34
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译：非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。非易失性半导体存储器还包括初始设置数据锁存器。在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。

6. 发明申请

US20060146607A1 Non-volatile semiconductor memory device 有权
公开(公告)号：US20060146607A1
公开(公告)日：2006-07-06
申请号：US11366110
申请日：2006-03-01
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

7. 发明授权

US06972996B2 Pattern layout of transfer transistors employed in row decoder 失效
公开(公告)号：US06972996B2
公开(公告)日：2005-12-06
申请号：US10922950
申请日：2004-08-23
申请人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
发明人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
IPC分类号： H01L21/8247 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C8/10 , G11C8/08 , G11C16/0483 , G11C16/08
摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

8. 发明授权

US06865112B2 Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays 有权
标题翻译：非易失性半导体存储器件，其中为多个存储单元阵列设置一页
公开(公告)号：US06865112B2
公开(公告)日：2005-03-08
申请号：US10795881
申请日：2004-03-08
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C16/02 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/3454
摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.
摘要翻译：提供多个存储单元阵列。每个存储单元阵列具有多个存储单元，并且存储单元连接到多个字线。对应于多个存储单元阵列，提供多个字线驱动电路和多个位线控制电路。每个字线驱动电路选择并驱动相应存储单元阵列的字线。每个位控制电路对预先写在相应的存储单元阵列的多个存储单元中的数据进行验证读取，并且基于一个对应的字线驱动电路的字线控制选择和驱动操作结果验证阅读。

9. 发明授权

US06859401B2 Fail number detecting circuit of flash memory 有权
标题翻译：闪存的故障号检测电路
公开(公告)号：US06859401B2
公开(公告)日：2005-02-22
申请号：US10674404
申请日：2003-10-01
申请人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
发明人： Koji Hosono , Tamio Ikehashi , Tomoharu Tanaka , Kenichi Imamiya , Hiroshi Nakamura , Ken Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/34 , G11C29/04 , G11C29/12
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.
摘要翻译：半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。存储单元阵列包括其中布置的NAND单元。锁存电路暂时保存从存储单元阵列读出的数据。第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。第二电路产生预置的第二电流。第三电路将第一电流与第二电流进行比较。基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

10. 发明申请

US20050018462A1 Pattern layout of transfer transistors employed in row decoder 失效
标题翻译：在行解码器中使用的转移晶体管的图案布局
公开(公告)号：US20050018462A1
公开(公告)日：2005-01-27
申请号：US10922950
申请日：2004-08-23
申请人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
发明人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya , Tomoharu Tanaka
IPC分类号： H01L21/8247 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/08 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C19/08
CPC分类号： G11C8/10 , G11C8/08 , G11C16/0483 , G11C16/08
摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.
摘要翻译：半导体器件包括存储单元阵列和字线选择电路。存储单元阵列包括以行和列排列的多个存储单元。存储单元阵列包括其中每个存储单元被布置的多个块。字线选择电路包括以列和列方向布置的传输晶体管，并且被配置为通过传输晶体管的电流路径将多个不同的电压传送到字线，并且选择所述多个块的至少一行的存储单元。转移晶体管包括第一组，其在写入操作中传送施加到字线的最低电压电压，第二组被布置为不与第一组相邻，并且传送施加到第一组的最高电压电压写字操作中的字线。

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