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1. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

2. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

3. 发明申请

US20080291743A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20080291743A1
公开(公告)日：2008-11-27
申请号：US12123791
申请日：2008-05-20
申请人： Toshiaki Edahiro , Masahiro Yoshihara
发明人： Toshiaki Edahiro , Masahiro Yoshihara
IPC分类号： G11C16/24 , G11C16/26
CPC分类号： G11C16/32 , G11C16/26
摘要： This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.
摘要翻译：本公开涉及包括位线的半导体存储装置; 向电池提供电荷的第一电容器; 第一感测节点发送对应于所述小区的数据的电位; 对位线充电的第一预充电部分，第一电容器和第一感测节点; 锁定数据的第一锁存部分; 第一感测部分，包括连接在电源和第一锁存部分之间的第一感测晶体管，栅极连接到第一感测节点; 以及将第一锁存部分和第一检测晶体管之间的第一节点连接到位线的第一钳位部分，其中第一电容器在检测期间将电荷提供给位线，并且第一感测部分从电源提供电荷响应于第一感测节点处的电位，经由第一钳位部分到位线。

4. 发明授权

US08107293B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08107293B2
公开(公告)日：2012-01-31
申请号：US13004926
申请日：2011-01-12
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

5. 发明授权

US07881120B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07881120B2
公开(公告)日：2011-02-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

6. 发明授权

US07692987B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07692987B2
公开(公告)日：2010-04-06
申请号：US12123791
申请日：2008-05-20
申请人： Toshiaki Edahiro , Masahiro Yoshihara
发明人： Toshiaki Edahiro , Masahiro Yoshihara
IPC分类号： G11C7/00
CPC分类号： G11C16/32 , G11C16/26
摘要： This disclosure concerns a semiconductor storage device including a bit line; a first capacitor supplying a charge to a cell; a first sense node transmitting a potential corresponding to data of the cell; a first pre-charge part charging the bit line, the first capacitor, and the first sense node; a first latch part latching the data; a first sense part including a first sense transistor connected between a power supply and the first latch part, the gate is connected to the first sense node; and a first clamp part connecting a first node between the first latch part and the first sense transistor to the bit line, wherein the first capacitor supplies the charge to the bit line during detecting, and the first sense part supplies a charge from the power supply to the bit line via the first clamp part in response a potential at the first sense node.
摘要翻译：本公开涉及包括位线的半导体存储装置; 向电池提供电荷的第一电容器; 第一感测节点发送对应于所述小区的数据的电位; 对位线充电的第一预充电部分，第一电容器和第一感测节点; 锁定数据的第一锁存部分; 第一感测部分，包括连接在电源和第一锁存部分之间的第一感测晶体管，栅极连接到第一感测节点; 以及将第一锁存部分和第一检测晶体管之间的第一节点连接到位线的第一钳位部分，其中第一电容器在检测期间将电荷提供给位线，并且第一感测部分从电源提供电荷响应于第一感测节点处的电位，经由第一钳位部分到位线。

7. 发明申请

US20090244978A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090244978A1
公开(公告)日：2009-10-01
申请号：US12408260
申请日：2009-03-20
申请人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro Yoshihara , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

8. 发明授权

US08923074B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08923074B2
公开(公告)日：2014-12-30
申请号：US13432465
申请日：2012-03-28
申请人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
发明人： Masahiro Yoshihara , Naofumi Abiko , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G11C7/106 , G11C7/1087 , G11C16/0483 , G11C16/26
摘要： A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group including one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer.
摘要翻译：感测放大器电路连接到位线，并感测并放大从存储器单元读取的信号。第一数据锁存器通过第一总线连接到读出放大器。第二数据锁存器连接到第二总线。多个电路组在第一方向上重复设置，每个电路组包括一个读出放大器电路和一个第一数据锁存器。第二数据锁存器设置在电路组和输入/输出缓冲器之间。

9. 发明授权

US08274845B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08274845B2
公开(公告)日：2012-09-25
申请号：US12793062
申请日：2010-06-03
申请人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
发明人： Katsumi Abe , Masahiro Yoshihara , Masaru Koyanagi
IPC分类号： G11C7/00 , G11C16/00
CPC分类号： G11C7/1078 , G11C7/1084 , G11C16/04 , G11C16/20 , G11C29/02 , G11C29/028 , G11C2207/2254
摘要： A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory.
摘要翻译：提供了一种非易失性半导体存储器件，其包括：输入缓冲器，其具有能够电调节电路阈值的第一反相器;电路：具有与第一反相器相同电路结构的第二反相器的阈值监视器，用于检测电路分别在第二反相器的输入和输出短路时第一反相器的阈值，存储与由电路阈值监视器检测的电路阈值对应的参数值的存储器，读取数据读取器电路的数据读取器电路从存储器给予第一反相器的参数值。

10. 发明授权

US08228744B2 Semiconductor memory device having sense amplifier 有权
标题翻译：具有读出放大器的半导体存储器件
公开(公告)号：US08228744B2
公开(公告)日：2012-07-24
申请号：US12693798
申请日：2010-01-26
申请人： Masahiro Yoshihara , Katsumi Abe
发明人： Masahiro Yoshihara , Katsumi Abe
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair.
摘要翻译：半导体存储器件包括存储单元阵列，页缓冲器，数据线对，差分放大器和预充电器。存储单元阵列包括多个存储单元布置在其中的多个页面。页面缓冲器形成在与存储单元阵列相邻的位置，并且包括多个读出放大器，被配置为临时保持从页面中的存储器单元读取的页面数据。数据线对被布置在页缓冲器中并连接到读出放大器。差分放大器被配置为放大数据线对的线之间的电位差。预充电器被配置为将数据线对预充电到预定电位。差分放大器和预充电器中的至少一个形成在页面缓冲器中，并且至少一个电路电连接到数据线对。

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