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1. 发明申请

US20070090433A1 Isolation collar void and methods of forming the same 审中-公开
标题翻译：隔离环空隙及其形成方法
公开(公告)号：US20070090433A1
公开(公告)日：2007-04-26
申请号：US11259295
申请日：2005-10-26
申请人： Kangguo Cheng , Herbert Ho , Jack Mandelman
发明人： Kangguo Cheng , Herbert Ho , Jack Mandelman
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L29/0657
摘要： In a first aspect, a first apparatus is provided. The first apparatus includes a void formed around one or more portions of a microelectronic device in a bulk substrate. The void is adapted to reduce a parasitic leakage between the microelectronic device and the bulk substrate. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置包括在体基板中的微电子器件的一个或多个部分周围形成的空隙。该空隙适于减少微电子器件与本体衬底之间的寄生泄漏。提供了许多其他方面。

2. 发明申请

US20070045686A1 Ferromagnetic memory cell and methods of making and using the same 有权
标题翻译：铁磁记忆单元及其制造和使用方法
公开(公告)号：US20070045686A1
公开(公告)日：2007-03-01
申请号：US11216387
申请日：2005-08-31
申请人： Kangguo Cheng , Herbert Ho , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Herbert Ho , Louis Hsu , Jack Mandelman
IPC分类号： H01L29/94
CPC分类号： G11C11/15 , H01L27/1203 , H01L43/065
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。提供了许多其他方面。

3. 发明申请

US20080064162A1 VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20080064162A1
公开(公告)日：2008-03-13
申请号：US11931238
申请日：2007-10-31
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

4. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

5. 发明申请

US20080042204A1 METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY 审中-公开
公开(公告)号：US20080042204A1
公开(公告)日：2008-02-21
申请号：US11924875
申请日：2007-10-26
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.

6. 发明申请

US20070247273A1 ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF 失效
公开(公告)号：US20070247273A1
公开(公告)日：2007-10-25
申请号：US11768254
申请日：2007-06-26
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： H01H85/06 , H01L21/336 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

7. 发明申请

US20070235833A1 Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
标题翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法
公开(公告)号：US20070235833A1
公开(公告)日：2007-10-11
申请号：US11393142
申请日：2006-03-30
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L29/00
CPC分类号： H01L27/10841 , H01L27/10864
摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.
摘要翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。半导体材料的中间区域分离第一和第二掺杂区域。第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料侧壁。

8. 发明申请

US20070210363A1 Vertical SOI transistor memory cell and method of forming the same 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20070210363A1
公开(公告)日：2007-09-13
申请号：US11308105
申请日：2006-03-07
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

9. 发明申请

US20070148836A1 Reduced-resistance finFETs and methods of manufacturing the same 有权
标题翻译：降低电阻finFET及其制造方法
公开(公告)号：US20070148836A1
公开(公告)日：2007-06-28
申请号：US11316244
申请日：2005-12-22
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman , Haining Yang
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823418 , H01L21/823437 , H01L29/41791 , H01L29/665 , H01L29/6653 , H01L29/66795 , H01L29/78618 , H01L2029/7858 , Y10S438/96
摘要： In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了制造finFET的第一种方法。第一种方法包括以下步骤：（1）提供衬底; 和（2）在所述衬底上形成所述finFET的至少一个源极/漏极扩散区域。每个源极/漏极扩散区域包括（a）非硅化硅的内部区域; 和（b）硅化物形成在非硅化硅区域的顶表面和侧壁上。提供了许多其他方面。

10. 发明申请

US20070099391A1 Methods for forming semiconductor structures with buried isolation collars and semiconductor structures formed by these methods 失效
标题翻译：用这些方法形成的具有掩埋隔离环和半导体结构的半导体结构的方法
公开(公告)号：US20070099391A1
公开(公告)日：2007-05-03
申请号：US11262128
申请日：2005-10-28
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/76
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls.
摘要翻译：包括形成在衬底中的沟槽和在沟槽的侧壁周围延伸的掩埋隔离环的半导体结构。埋置的隔离环由由基底材料的埋入多孔区形成的绝缘体构成。多孔区域由掩蔽和离子注入限定的掩埋掺杂区域或通过掩蔽沟槽侧壁并使用掺杂剂扩散形成。有利地，多孔区域通过氧化工艺转变成氧化物绝缘体。半导体结构可以是存储单元的存储电容器，其还具有围绕沟槽的掩埋板和沟槽内的电容器节点，其通过形成在沟槽侧壁上的节点电介质与掩埋板分离。

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