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1. 发明授权

US07482225B2 Method of fabricating floating gate of flash memory device 失效
标题翻译：制造闪存器件浮栅的方法
公开(公告)号：US07482225B2
公开(公告)日：2009-01-27
申请号：US11473690
申请日：2006-06-23
申请人： Kang Hyun Lee , Jeong Yel Jang
发明人： Kang Hyun Lee , Jeong Yel Jang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273
摘要： A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning the photoresist; forming polymer sidewalls on the sides of the patterned photoresist; and selectively removing the conductive thin layer using the photoresist and the polymer sidewalls as a mask to form a floating gate.
摘要翻译：提供一种制造闪速存储器件的浮动栅极的方法。该方法包括：在衬底上形成隧穿氧化物层; 在隧道氧化物层上形成导电薄层; 在导电薄层上施加光致抗蚀剂; 通过图案化光致抗蚀剂来限定浮栅区域; 在图案化的光致抗蚀剂的侧面上形成聚合物侧壁; 并且使用光致抗蚀剂和聚合物侧壁作为掩模选择性地去除导电薄层，以形成浮栅。

2. 发明授权

US07405161B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07405161B2
公开(公告)日：2008-07-29
申请号：US11320977
申请日：2005-12-30
申请人： Jeong Yel Jang , Kang Hyun Lee
发明人： Jeong Yel Jang , Kang Hyun Lee
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/28 , H01L21/3213
CPC分类号： H01L21/32139 , H01L21/31116 , H01L21/31138
摘要： Method for fabricating a semiconductor device in which a by-product of etching is deposited on a photoresist film for using as a mask. The method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in succession, forming a photoresist film pattern on a predetermined portion of the bottom anti-refection coating, etching the bottom anti-refection coating by using the photoresist film pattern to deposit by-product of the etching on sidewalls of the photoresist pattern to form spacers, and etching the polysilicon by using the photoresist film pattern and the spacers, to form a line.
摘要翻译：制造半导体器件的方法，其中蚀刻副产物沉积在用作掩模的光致抗蚀剂膜上。制造半导体器件的方法包括以下步骤：在基片的整个表面上依次沉积多晶硅和底部抗反射涂层，在底部抗反射涂层的预定部分上形成光致抗蚀剂膜图案，蚀刻通过使用光致抗蚀剂膜图案沉积蚀刻的副产物的底部抗反射涂层以形成间隔物，并且通过使用光致抗蚀剂膜图案和间隔物蚀刻多晶硅以形成线。

3. 发明授权

US07678677B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07678677B2
公开(公告)日：2010-03-16
申请号：US11880473
申请日：2007-07-20
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a semiconductor device includes: forming a device isolation layer in a semiconductor substrate; forming a gate insulating layer and a gate electrode on the semiconductor substrate; depositing a triple layer over the resulting structure, the triple layer including a bottom oxide layer, a nitride oxide layer and a top oxide layer; and etching the triple layer to form spacers.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底中形成器件隔离层; 在半导体衬底上形成栅极绝缘层和栅电极; 在所得结构上沉积三层，所述三层包括底部氧化物层，氮化物氧化物层和顶部氧化物层; 并蚀刻三层以形成间隔物。

4. 发明申请

US20090115068A1 Semiconductor Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090115068A1
公开(公告)日：2009-05-07
申请号：US12251726
申请日：2008-10-15
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/522 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the same. In the method, a metal interconnection can be formed on a substrate. A dielectric can be formed on the metal interconnection. A photoresist pattern can be formed on the dielectric. The dielectric can be etched using the photoresist pattern as an etch mask to form a dense region of contact holes exposing the metal interconnection and dummy patterns surrounding the region of contact holes. In the semiconductor device, the dummy patterns are disposed around the dense contact holes to minimize a difference between etching rates of the contact holes, thereby inhibiting an etching defect such as an under-etch or over-etch defect.
摘要翻译：提供半导体器件及其制造方法。在该方法中，可以在基板上形成金属互连。电介质可以形成在金属互连上。可以在电介质上形成光致抗蚀剂图案。可以使用光致抗蚀剂图案作为蚀刻掩模来蚀刻电介质，以形成暴露金属互连和接触孔区域周围的虚拟图案的接触孔的致密区域。在半导体器件中，虚设图案设置在致密接触孔周围，以最小化接触孔的蚀刻速率之间的差异，从而抑制诸如蚀刻不足或过蚀刻缺陷之类的蚀刻缺陷。

5. 发明授权

US07829367B2 Image sensor and method for manufacturing the same 失效
公开(公告)号：US07829367B2
公开(公告)日：2010-11-09
申请号：US12654489
申请日：2009-12-22
申请人： Sang Il Hwang , Jeong Yel Jang
发明人： Sang Il Hwang , Jeong Yel Jang
IPC分类号： H01L21/00 , H01L31/00
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14627
摘要： An image sensor and a method for manufacturing the same are provided. In the method, a photoresist is formed on a substrate including a photodiode region and a gate electrode opposite to the photodiode region on the basis of the gate electrode. An oxide layer is formed to a specific thickness on both the photodiode region and a part of the gate electrode. The photoresist is removed from the substrate and cleaned. A first oxide film is formed on the substrate, the gate electrode, and the oxide layer remaining on the photodiode region. A nitride film is formed on the first oxide film. And a second oxide film is formed on the nitride film. Blank etching is performed on the first oxide film, the nitride film, and the second oxide film to form a spacer at the side of the gate electrode.

6. 发明申请

US20070154852A1 METHOD FOR PATTERNING A THIN FILM USING A PLASMA BY-PRODUCT 审中-公开
标题翻译：使用等离子体副产品形成薄膜的方法
公开(公告)号：US20070154852A1
公开(公告)日：2007-07-05
申请号：US11617186
申请日：2006-12-28
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： G03F7/26
CPC分类号： H01L21/32139 , H01L21/0212 , H01L21/02274 , H01L21/0274 , H01L21/3127
摘要： Embodiments relate to a method of patterning a thin film using a by-product of plasma. According to embodiments, the method may include (a) forming a thin film serving as a target object to be etched on a substrate, (b) forming photoresist patterns on the thin film, (c) performing a plasma treatment with respect to the photoresist pattern such that a by-product is attached to an outer wall of the photoresist pattern, and (d) patterning the thin film by using the photoresist patterns attached with the by-product as an etching mask. In embodiments, when a by-product of plasma is attached to a photoresist pattern such that the by-product of plasma is used as an etching mask, the thickness of the by-product may be formed as a desired thickness by controlling process variables.
摘要翻译：实施例涉及使用等离子体的副产物构图薄膜的方法。根据实施例，该方法可以包括：（a）在基板上形成用作待蚀刻目标物体的薄膜，（b）在薄膜上形成光刻胶图案，（c）对光致抗蚀剂进行等离子体处理使得副产物附着到光致抗蚀剂图案的外壁上，以及（d）通过使用附加有副产物的光致抗蚀剂图案作为蚀刻掩模来图案化薄膜。在实施方案中，当将等离子体的副产物连接到光致抗蚀剂图案上使得等离子体的副产物用作蚀刻掩模时，副产物的厚度可以通过控制工艺变量形成为期望的厚度。

7. 发明授权

US07741211B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07741211B2
公开(公告)日：2010-06-22
申请号：US11777101
申请日：2007-07-12
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device can include a first interlayer dielectric layer disposed on a substrate, and an air gap defined in a portion of the first interlayer dielectric layer. The air gap can be formed within trenches etched into the first interlayer dielectric layer. An etch stop layer is disposed on the first interlayer dielectric layer and the air gap, and includes a hole communicating with the air gap.
摘要翻译：半导体器件可以包括设置在衬底上的第一层间电介质层和限定在第一层间电介质层的一部分中的气隙。气隙可以形成在蚀刻到第一层间介质层的沟槽内。蚀刻停止层设置在第一层间介电层和气隙上，并且包括与气隙连通的孔。

8. 发明授权

US07635649B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07635649B2
公开(公告)日：2009-12-22
申请号：US11605552
申请日：2006-11-28
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/28 , H01L21/3213
CPC分类号： G03F7/40 , G03F7/091 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a polysilicon layer on a semiconductor substrate, forming an anti-reflection coating on the polysilicon layer, forming a photoresist (PR) layer pattern on the anti-reflection coating, etching the anti-reflection coating using the PR layer pattern as a mask in capacitive coupled plasma (CCP) equipment using CF4, Ar, and O2, so as to cause a reaction by-product generated by etching the anti-reflect coating to be deposited on sidewalls of the PR layer pattern, thereby forming spacers, and etching the polysilicon layer using the PR layer pattern and the spacers as a mask.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在半导体衬底上形成多晶硅层，在多晶硅层上形成抗反射涂层，在抗反射涂层上形成光致抗蚀剂（PR）层图案，使用PR层图案蚀刻抗反射涂层在使用CF4，Ar和O2的电容耦合等离子体（CCP）设备中的掩模，以便通过蚀刻抗反射涂层而产生的副产物沉积在PR层图案的侧壁上，从而形成间隔物，并使用PR层图案和间隔物作为掩模蚀刻多晶硅层。

9. 发明授权

US07592253B2 Method for forming a damascene pattern of a copper metallization layer 失效
标题翻译：用于形成铜金属化层的镶嵌图案的方法
公开(公告)号：US07592253B2
公开(公告)日：2009-09-22
申请号：US11644888
申请日：2006-12-26
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76813
摘要： There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.
摘要翻译：提供了在形成铜金属互连的镶嵌工艺中形成包括通孔和沟槽的镶嵌图案的方法。该方法包括在衬底上形成层间电介质层，形成包括第一开口的第一感光层图案，该第一感光层图案在层间电介质层上暴露要形成通孔的区域，使用所述第一感光层图案作为蚀刻掩模，去除所述第一感光层图案并形成第二感光层图案，所述第二感光层图案包括在所述层间介电层上暴露要形成沟槽的区域的第二开口，以及蚀刻所述层间电介质层，使用第二感光层图案作为蚀刻掩模，以同时形成通孔和沟槽。

10. 发明申请

US20070155170A1 Method for forming a damascene pattern of a copper metallization layer 失效
标题翻译：用于形成铜金属化层的镶嵌图案的方法
公开(公告)号：US20070155170A1
公开(公告)日：2007-07-05
申请号：US11644888
申请日：2006-12-26
申请人： Jeong Yel Jang
发明人： Jeong Yel Jang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76813
摘要： There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.
摘要翻译：提供了在形成铜金属互连的镶嵌工艺中形成包括通孔和沟槽的镶嵌图案的方法。该方法包括在衬底上形成层间电介质层，形成包括第一开口的第一感光层图案，该第一感光层图案在层间电介质层上暴露要形成通孔的区域，使用所述第一感光层图案作为蚀刻掩模，去除所述第一感光层图案并形成第二感光层图案，所述第二感光层图案包括在所述层间介电层上暴露要形成沟槽的区域的第二开口，以及蚀刻所述层间电介质层，使用第二感光层图案作为蚀刻掩模，以同时形成通孔和沟槽。

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