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1. 发明授权

US06869829B2 Semiconductor chip, chip-on-chip structure device, and assembling method thereof 有权
标题翻译：半导体芯片，片上芯片结构器件及其组装方法
公开(公告)号：US06869829B2
公开(公告)日：2005-03-22
申请号：US10211308
申请日：2002-08-05
申请人： Junichi Hikita , Koji Yamamoto , Isamu Nishimura , Nobuhisa Kumamoto
发明人： Junichi Hikita , Koji Yamamoto , Isamu Nishimura , Nobuhisa Kumamoto
IPC分类号： H01L23/544 , H01L21/60
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54473 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15151 , Y10S438/975 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).
摘要翻译：为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3））可以根据电极标记（35）容易地将前表面向下定位。

2. 发明授权

US06476499B1 Semiconductor chip, chip-on-chip structure device and assembling method thereof 有权
标题翻译：半导体芯片，片上芯片结构器件及其组装方法
公开(公告)号：US06476499B1
公开(公告)日：2002-11-05
申请号：US09499579
申请日：2000-02-07
申请人： Junichi Hikita , Koji Yamamoto , Isamu Nishimura , Nobuhisa Kumamoto
发明人： Junichi Hikita , Koji Yamamoto , Isamu Nishimura , Nobuhisa Kumamoto
IPC分类号： H01L2352
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/5442 , H01L2223/54473 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15151 , Y10S438/975 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor chip (3) to be positioned with a front face thereof downward for formation of a chip-on-chip structure has electrode marks (35) provided on a back face (34) thereof. The electrode marks (35) are respectively provided in association with a plurality of electrodes (33) provided on the front face (31) of the semiconductor chip in the same arrangement as the arrangement of the electrodes (33). The arrangement of the electrode marks (35) represents the arrangement of the electrodes (33) on the front face (31) when viewed from the side of the back face (34) of the semiconductor chip 3. Therefore, the semiconductor chip (3) can easily be positioned with the front face downward on the basis of the electrode marks (35).
摘要翻译：为了形成片上芯片结构，其前表面向下定位的半导体芯片（3）具有设置在其背面（34）上的电极标记（35）。电极标记（35）与设置在半导体芯片的正面（31）上的多个电极（33）分别设置成与电极（33）的布置相同的布置。电极标记（35）的布置表示从半导体芯片3的背面（34）的侧面观察时的正面（31）上的电极（33）的配置。因此，半导体芯片（3））可以根据电极标记（35）容易地将前表面向下定位。

3. 发明授权

US06404061B1 Semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片
公开(公告)号：US06404061B1
公开(公告)日：2002-06-11
申请号：US09512061
申请日：2000-02-24
申请人： Junichi Hikita , Isamu Nishimura , Nobuhisa Kumamoto , Yoshiyasu Morishima
发明人： Junichi Hikita , Isamu Nishimura , Nobuhisa Kumamoto , Yoshiyasu Morishima
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/00014
摘要： A semiconductor device having a solid device, and a semiconductor chip bonded to the solid device with a back face thereof being opposed to a front face of the solid device. The semiconductor chip has a back electrode provided on the back face thereof and electrically connected to an electrode provided on a front face thereof through a through-hole. The solid device may be a wiring board or another semiconductor chip. Further another semiconductor chip may be stacked and bonded onto the front face of the semiconductor chip.
摘要翻译：具有固体器件的半导体器件和与固体器件接合的半导体芯片，其背面与固体器件的正面相对。半导体芯片具有设置在其背面上的背电极，并且通过通孔与设置在其正面上的电极电连接。固体器件可以是布线板或另一半导体芯片。另外的另一半导体芯片可以堆叠并结合到半导体芯片的正面上。

4. 发明申请

US20110298044A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110298044A1
公开(公告)日：2011-12-08
申请号：US13214271
申请日：2011-08-22
申请人： Ryotaro YAGI , Isamu Nishimura , Takahisa Yamaha
发明人： Ryotaro YAGI , Isamu Nishimura , Takahisa Yamaha
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/7813 , H01L21/76202 , H01L21/76224 , H01L21/76264 , H01L29/0649 , H01L29/4236 , H01L29/42376 , H01L29/4916 , H01L29/66659 , H01L29/66734 , H01L29/7835
摘要： The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.
摘要翻译：根据本发明的半导体器件包括半导体层，通过从其表面挖掘半导体层而形成的沟槽，形成在沟槽的内表面上的栅极绝缘膜和嵌入沟槽中的由硅制成的栅电极通过栅极绝缘膜。栅电极具有形成为以相对高的导电率覆盖栅极绝缘膜的高导电性部分和形成在导电性较差的高导电性部分内的区域的低导电性部分。

5. 发明授权

US08044491B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08044491B2
公开(公告)日：2011-10-25
申请号：US12805167
申请日：2010-07-15
申请人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
发明人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.
摘要翻译：根据本发明的半导体器件包括由金属材料制成的下电极，由绝缘材料制成并层压在下电极上的电容膜，由金属材料制成的上电极，通过电容与下电极相对膜，并且在相对方向的平面图中具有比下部电极的轮廓小的轮廓，以及由与电容膜相同的材料制成并层压在上部电极上的保护膜。

6. 发明授权

US06251797B1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06251797B1
公开(公告)日：2001-06-26
申请号：US09515670
申请日：2000-02-29
申请人： Isamu Nishimura
发明人： Isamu Nishimura
IPC分类号： H01L2100
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05572 , H01L2224/13099 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941
摘要： In the present invention, an electrode having a structure in which a barrier layer 16 and a seed layer 17 are stacked on an electrode 12b is formed. In the electrode having such a structure, when an Al wiring film is formed, the barrier layer 16 and the seed layer 17 may be stacked by sputtering after the wiring film is formed. That is, at the time of forming wiring, the barrier layer 16 and the seed layer 17 may be stacked on the surface of the wiring. Accordingly, the formation of a bump and particularly, the formation of the seed layer for the bump are performed together with the wiring formation and protective film formation processing. Accordingly, the steps of fabricating a semiconductor are simplified, so that a time period required for the fabrication is shortened.
摘要翻译：在本发明中，形成了具有阻挡层16和种子层17层叠在电极12b上的结构的电极。在具有这种结构的电极中，当形成Al布线膜时，可以在形成布线膜之后通过溅射层叠阻挡层16和籽晶层17。也就是说，在形成布线时，阻挡层16和种子层17可以堆叠在布线的表面上。因此，与布线形成和保护膜形成处理一起进行突起的形成，特别是凸起的种子层的形成。因此，简化了制造半导体的步骤，从而缩短了制造所需的时间。

7. 发明授权

US07781863B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07781863B2
公开(公告)日：2010-08-24
申请号：US12007084
申请日：2008-01-07
申请人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
发明人： Ryotaro Yagi , Yuichi Nakao , Isamu Nishimura
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.

8. 发明授权

US07994585B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07994585B2
公开(公告)日：2011-08-09
申请号：US12318861
申请日：2009-01-09
申请人： Isamu Nishimura
发明人： Isamu Nishimura
IPC分类号： H01L21/70
CPC分类号： H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention includes: a semiconductor layer; an element separating portion, formed in a top layer portion of the semiconductor layer and separating, in the semiconductor layer, a first element forming region for forming a first conductive type MOSFET and a second element forming region for forming a second conductive type MOSFET; a first gate insulating film, selectively formed on a top surface of the semiconductor layer in the first element forming region; a first gate electrode, formed on the first gate insulating film; a first sidewall, formed at a periphery of the first gate insulating film and the first gate electrode; a second gate insulating film, selectively formed on a top surface of the semiconductor layer in the second element forming region; a second gate electrode, formed on the second gate insulating film; and a second sidewall, formed at a periphery of the second gate insulating film and the second gate electrode. The first sidewall includes: a base, contacting the top surface of the semiconductor layer; and a main body, formed on the base and protruding laterally beyond a peripheral edge of the base.
摘要翻译：根据本发明的半导体器件包括：半导体层; 元件分离部分，形成在所述半导体层的顶层部分中，并且在所述半导体层中分离用于形成第一导电型MOSFET的第一元件形成区域和用于形成第二导电型MOSFET的第二元件形成区域; 第一栅极绝缘膜，选择性地形成在第一元件形成区域中的半导体层的顶表面上; 形成在第一栅极绝缘膜上的第一栅电极; 第一侧壁，形成在第一栅极绝缘膜和第一栅电极的周边; 第二栅极绝缘膜，选择性地形成在所述第二元件形成区域中的所述半导体层的顶表面上; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在所述第二栅极绝缘膜和所述第二栅电极的周围的第二侧壁。第一侧壁包括：与半导体层的顶表面接触的基底; 以及主体，形成在基部上并且横向突出超过基部的周缘。

9. 发明申请

US20090140330A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090140330A1
公开(公告)日：2009-06-04
申请号：US12314067
申请日：2008-12-03
申请人： Ryotaro Yagi , Isamu Nishimura , Takahisa Yamaha
发明人： Ryotaro Yagi , Isamu Nishimura , Takahisa Yamaha
IPC分类号： H01L29/78 , H01L21/336 , H01L21/283 , H01L29/06
CPC分类号： H01L29/7813 , H01L21/76202 , H01L21/76224 , H01L21/76264 , H01L29/0649 , H01L29/4236 , H01L29/42376 , H01L29/4916 , H01L29/66659 , H01L29/66734 , H01L29/7835
摘要： The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.
摘要翻译：根据本发明的半导体器件包括半导体层，通过从其表面挖掘半导体层而形成的沟槽，形成在沟槽的内表面上的栅极绝缘膜和嵌入沟槽中的由硅制成的栅电极通过栅极绝缘膜。栅电极具有形成为以相对高的导电率覆盖栅极绝缘膜的高导电性部分和形成在导电性较差的高导电性部分内的区域的低导电性部分。

10. 发明申请

US20050001267A1 Semiconductor device having a damascene-type gate or a replacing-type gate and method of manufacturing the same 失效
标题翻译：具有镶嵌型栅极或替代型栅极的半导体器件及其制造方法
公开(公告)号：US20050001267A1
公开(公告)日：2005-01-06
申请号：US10863395
申请日：2004-06-09
申请人： Kazuhiro Miyagawa , Mitsuo Yasuhira , Yasushi Akasaka , Isamu Nishimura
发明人： Kazuhiro Miyagawa , Mitsuo Yasuhira , Yasushi Akasaka , Isamu Nishimura
IPC分类号： H01L29/423 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L23/52 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/41 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/823878 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.
摘要翻译：半导体器件包括半导体元件和至少一个虚设图案。每个或至少一些半导体元件具有镶嵌栅极结构或替代栅极结构，并且位于元件形成区域中。此外，至少一个虚拟图案位于与元件形成区域不同的区域中。虚设图案可以具有与大马士革栅极结构相同或不同种类的半导体元件结构或替代栅极结构。虚设图案可以是绝缘膜，接口晶体管或模拟电路电容器电极的图案，而不是虚拟栅极。

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