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1. 发明申请

US20110279135A1 MEMRISTOR ADJUSTMENT USING STORED CHARGE 审中-公开
标题翻译：使用存储充电器进行调整
公开(公告)号：US20110279135A1
公开(公告)日：2011-11-17
申请号：US12781441
申请日：2010-05-17
申请人： Julien Borghetti , Bilberto Medeiros Ribeiro , Dmitri Borisovich Strukov
发明人： Julien Borghetti , Bilberto Medeiros Ribeiro , Dmitri Borisovich Strukov
IPC分类号： G01R27/08
CPC分类号： G01R31/2637 , G11C13/0002 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： Methods and apparatus pertaining to memory resistors are provided. Electronic circuitry determines energy for changing a non-volatile resistance of a memristor from a present value to a target value. An electric charge corresponding to the energy is stored. An electric pulse is applied to the memristor using the stored charge. The newly adjusted resistance of the memristor is sensed and compared to the target value. Additional electric pulses can be applied in accordance with the comparison. Memristor adjustment by way of feedback control is thus contemplated by the present teachings.
摘要翻译：提供了与存储电阻有关的方法和装置。电子电路确定用于将忆阻器的非易失性电阻从当前值改变为目标值的能量。存储对应于能量的电荷。使用存储的电荷将电脉冲施加到忆阻器。忆阻器的新调节电阻被感测并与目标值进行比较。根据比较可以应用额外的电脉冲。因此通过反馈控制进行的忆阻器调节由本教导设想。

2. 发明授权

US09793275B2 Multilayer circuit 有权
公开(公告)号：US09793275B2
公开(公告)日：2017-10-17
申请号：US13259177
申请日：2009-08-14
申请人： Dmitri Borisovich Strukov , Julien Borghetti
发明人： Dmitri Borisovich Strukov , Julien Borghetti
IPC分类号： H01L23/48 , H01L29/792 , H01L23/52 , H01L21/44 , H01L27/105 , H01L27/06 , H01L27/10 , H01L27/112 , H01L27/24
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/101 , H01L27/112 , H01L27/11286 , H01L27/24
摘要： A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first overlying layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215). The second overlying layer (220) has a second routing section (210) and is formed using the same set of masks. The first routing section (210) and the second routing section (210) form a unique electrical pathway (248) between a base via (247) and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

3. 发明申请

US20120032345A1 MULTILAYER CIRCUIT 有权
标题翻译：多层电路
公开(公告)号：US20120032345A1
公开(公告)日：2012-02-09
申请号：US13259177
申请日：2009-08-14
申请人： Dmitri Borisovich Strukov , Julien Borghetti
发明人： Dmitri Borisovich Strukov , Julien Borghetti
IPC分类号： H01L23/48
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/101 , H01L27/112 , H01L27/11286 , H01L27/24
摘要： A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215). The second overlying layer (220) has a second routing section (210)
摘要翻译：多层电路（400）包括具有多个基极通孔（247,415）的基底层（205），形成在基底层（205）上的第一层（215），并具有第一路由部分（210）和形成在第一覆盖层（215）上的第二覆盖层（220）。第二覆盖层（220）具有第二路由部分（210）

4. 发明申请

US20120001654A1 Three Dimensional Multilayer Circuit 有权
标题翻译：三维多层电路
公开(公告)号：US20120001654A1
公开(公告)日：2012-01-05
申请号：US13256233
申请日：2009-04-06
申请人： Dmitri Borisovich Strukov , R. Stanley Williams
发明人： Dmitri Borisovich Strukov , R. Stanley Williams
IPC分类号： H03K19/177 , H01L21/82
CPC分类号： H01L27/101 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A three dimensional multilayer circuit (400) includes a via array (325, 330) made up of a set of first vias (325) and a set of second vias (330) and an area distributed CMOS layer (310) configured to selectively address said first vias (325) and said second vias (330). At least two crossbar arrays (305, 420) overlay the area distributed CMOS layer (310). These crossbar arrays (305, 420) include a plurality of intersecting crossbar segments (320, 322) and programmable cross-point devices (315) which are interposed between the intersecting crossbar segments (320, 322). The vias (325, 330) are connected to the crossbar segments (320, 322) such that each programmable crosspoint devices (315) can be uniquely accessed using a first via (325) and a second via (330).
摘要翻译：三维多层电路（400）包括由一组第一通孔（325）和一组第二通孔（330）组成的通孔阵列（325,330）和区域分布式CMOS层（310），其被配置为选择性地寻址所述第一通孔（325）和所述第二通孔（330）。至少两个横杆阵列（305,420）覆盖区域分布式CMOS层（310）。这些横杆阵列（305,420）包括多个交叉横截面段（320,322）和可编程交叉点设备（315），它们插入在相交的横杆段（320,322）之间。通孔（325,330）连接到横杆段（320,322），使得可以使用第一通孔（325）和第二通孔（330）唯一地访问每个可编程交叉点设备（315）。

5. 发明申请

US20110095774A1 TESTING A NONVOLATILE CIRCUIT ELEMENT HAVING MULTIPLE INTERMEDIATE STATES 有权
标题翻译：测试具有多个中间状态的非线性电路元件
公开(公告)号：US20110095774A1
公开(公告)日：2011-04-28
申请号：US12605441
申请日：2009-10-26
申请人： Matthew D. Pickett , Dmitri Borisovich Strukov
发明人： Matthew D. Pickett , Dmitri Borisovich Strukov
IPC分类号： G01R31/3187 , G01R31/02 , G01R1/06
CPC分类号： G11C29/50 , G01R31/2637 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C16/04 , G11C29/50008 , G11C2013/0073
摘要： A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.
摘要翻译：测试电路测试具有多个中间状态的非易失性电路元件。测试电路包括波形发生器，其被配置为向连接到测试电路的电路元件施加波形。波形包括随时间施加到电路元件的应力脉冲。当波形被施加到电路元件时，检测器检测电路元件的参数。

6. 发明授权

US08373440B2 Three dimensional multilayer circuit 有权
标题翻译：三维多层电路
公开(公告)号：US08373440B2
公开(公告)日：2013-02-12
申请号：US13256233
申请日：2009-04-06
申请人： Dmitri Borisovich Strukov , R. Stanley Williams
发明人： Dmitri Borisovich Strukov , R. Stanley Williams
IPC分类号： H03K19/173
CPC分类号： H01L27/101 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A three dimensional multilayer circuit includes a via array made up of a set of first vias and a set of second vias and an area distributed CMOS layer configured to selectively address said first vias and said second vias. At least two crossbar arrays overlay the area distributed CMOS layer. These crossbar arrays include a plurality of intersecting crossbar segments and programmable crosspoint devices which are interposed between the intersecting crossbar segments. The vias are connected to the crossbar segments such that each programmable crosspoint devices can be uniquely accessed using a first via and a second via.
摘要翻译：三维多层电路包括由一组第一通孔和一组第二通孔构成的通孔阵列以及被配置为选择性地寻址所述第一通孔和所述第二通孔的区域分布式CMOS层。至少两个横杆阵列覆盖区域分布式CMOS层。这些横杆阵列包括多个相交的横杆段和可插入交叉横截面段之间的可编程交叉点装置。通孔连接到横杆段，使得可以使用第一通孔和第二通孔来唯一地访问每个可编程的交叉点设备。

7. 发明授权

US08310252B2 Testing a nonvolatile circuit element having multiple intermediate states 有权
标题翻译：测试具有多个中间状态的非易失性电路元件
公开(公告)号：US08310252B2
公开(公告)日：2012-11-13
申请号：US12605441
申请日：2009-10-26
申请人： Matthew D Pickett , Dmitri Borisovich Strukov
发明人： Matthew D Pickett , Dmitri Borisovich Strukov
IPC分类号： G01R31/3187 , G01R31/02
CPC分类号： G11C29/50 , G01R31/2637 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C16/04 , G11C29/50008 , G11C2013/0073
摘要： A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.
摘要翻译：测试电路测试具有多个中间状态的非易失性电路元件。测试电路包括波形发生器，其被配置为向连接到测试电路的电路元件施加波形。波形包括随时间施加到电路元件的应力脉冲。当波形被施加到电路元件时，检测器检测电路元件的参数。

8. 发明授权

US08530880B2 Reconfigurable multilayer circuit 有权
标题翻译：可重构多层电路
公开(公告)号：US08530880B2
公开(公告)日：2013-09-10
申请号：US13259168
申请日：2009-07-27
申请人： Dmitri Borisovich Strukov , R. Stanley Williams , Yevgeniy Eugene Shteyn
发明人： Dmitri Borisovich Strukov , R. Stanley Williams , Yevgeniy Eugene Shteyn
IPC分类号： H01L29/06 , H03K19/177 , H03K25/00 , H03K19/173
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/101 , H01L27/105
摘要： A reconfigurable multilayer circuit (400) includes a complimentary metal-oxide-semiconductor (CMOS) layer (210) having control circuitry, logic gates (515), and at least two crossbar arrays (205, 420) which overlie the CMOS layer (210). The at least two crossbar arrays (205, 420) are configured by the control circuitry and form reconfigurable interconnections between the logic gates (515) within the CMOS layer (210).
摘要翻译：可重构多层电路（400）包括具有控制电路，逻辑门（515）和覆盖在CMOS层（210）上的至少两个交叉阵列（205,420）的互补金属氧化物半导体（CMOS）层（210））。所述至少两个横杆阵列（205,420）由所述控制电路配置并在所述CMOS层（210）内的所述逻辑门（515）之间形成可重构互连。

9. 发明授权

US08390323B2 Dense nanoscale logic circuitry 有权
标题翻译：密集的纳米级逻辑电路
公开(公告)号：US08390323B2
公开(公告)日：2013-03-05
申请号：US13256234
申请日：2009-04-30
申请人： Dmitri Borisovich Strukov , Philip J. Kuekes
发明人： Dmitri Borisovich Strukov , Philip J. Kuekes
IPC分类号： H03K19/177
CPC分类号： H01L27/24 , B82Y10/00
摘要： One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
摘要翻译：本发明的一个实施方案涉及包含微尺度层的混合纳米尺度/微米级器件，所述微米级层包括微米级和/或亚微米级电路部件，并且通过界面表面提供微米级或亚微米级引脚阵列; 以及在纳米尺度层内与微米级层相接触的至少两个纳米层子层，每个纳米级层子层含有规则间隔的平行纳米线，所述至少两个纳米级子层的每个纳米线在电与由微尺度层提供的至多一个引脚接触，具有不同方向的连续纳米级子层的平行纳米线与连续的纳米级层子层的纳米线相交以形成可编程的交叉点。

10. 发明申请

US20120001653A1 Dense Nanoscale Logic Circuitry 有权
标题翻译：密集的纳米级逻辑电路
公开(公告)号：US20120001653A1
公开(公告)日：2012-01-05
申请号：US13256234
申请日：2009-04-30
申请人： Dmitri Borisovich Strukov , Philip J. Kuekes
发明人： Dmitri Borisovich Strukov , Philip J. Kuekes
IPC分类号： H03K19/173 , B82Y99/00
CPC分类号： H01L27/24 , B82Y10/00
摘要： One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.
摘要翻译：本发明的一个实施方案涉及包含微尺度层的混合纳米尺度/微米级器件，所述微米级层包括微米级和/或亚微米级电路部件，并且通过界面表面提供微米级或亚微米级引脚阵列; 以及在纳米尺度层内与微米级层相接触的至少两个纳米层子层，每个纳米级层子层含有规则间隔的平行纳米线，所述至少两个纳米级子层的每个纳米线在电与由微尺度层提供的至多一个引脚接触，具有不同方向的连续纳米级子层的平行纳米线与连续的纳米级层子层的纳米线相交以形成可编程的交叉点。

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