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1. 发明申请

US20070030729A1 METHOD OF SENSING AN EEPROM REFERENCE CELL 有权
标题翻译：传感EEPROM参考电池的方法
公开(公告)号：US20070030729A1
公开(公告)日：2007-02-08
申请号：US11198469
申请日：2005-08-05
申请人： Johnny Chan , Jinshu Son , Philip Ng
发明人： Johnny Chan , Jinshu Son , Philip Ng
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/28
摘要： An array of memory cells having a predetermined group of storage cells, arranged in a row, also have an arrangement of one or more reference cells fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.
摘要翻译：排列成行的具有预定组的存储单元的存储单元阵列还具有制造为与存储单元行相邻或邻近的一个或多个参考单元的布置。当存储单元写入，擦除或编程时，参考单元被写入，擦除或编程。相同数量的写，擦除或程序周期以及参考单元与存储单元的接近度保持了存储单元和参考单元的操作匹配。

2. 发明申请

US20060236044A1 Method and system for enhancing the endurance of memory cells 有权
公开(公告)号：US20060236044A1
公开(公告)日：2006-10-19
申请号：US11453953
申请日：2006-06-14
申请人： Johnny Chan , Philip Ng , Tinwai Wong
发明人： Johnny Chan , Philip Ng , Tinwai Wong
IPC分类号： G06F13/28
CPC分类号： G11C16/349
摘要： An integrated circuit device includes a plurality of non-volatile memory cells associated with a plurality of flag cells storing managing data. The managing data of the flag cells forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells to write new data and from which of the memory cells to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.

3. 发明授权

US07519486B2 Method and apparatus to test the power-on-reset trip point of an integrated circuit 有权
标题翻译：测试集成电路的上电复位跳变点的方法和装置
公开(公告)号：US07519486B2
公开(公告)日：2009-04-14
申请号：US11278223
申请日：2006-03-31
申请人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
发明人： Philip Ng , Jinshu Son , Liqi Wang , Johnny Chan
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G01R31/40 , G01R31/3004
摘要： Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
摘要翻译：用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。集成电路的第二I / O焊盘耦合到驱动器电路的输出端。可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

4. 发明授权

US07304514B2 Methods and circuits for sensing on-chip voltage in powerup mode 有权
标题翻译：用于在上电模式下检测片上电压的方法和电路
公开(公告)号：US07304514B2
公开(公告)日：2007-12-04
申请号：US11399848
申请日：2006-04-06
申请人： Johnny Chan , Philip Ng
发明人： Johnny Chan , Philip Ng
IPC分类号： H03L7/00
CPC分类号： H03K5/24
摘要： A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.
摘要翻译：用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

5. 发明申请

US20070236259A1 METHOD AND CIRCUITS FOR SENSING ON-CHIP VOLTAGE IN POWERUP MODE 有权
标题翻译：用于在电源模式下感测片上电压的方法和电路
公开(公告)号：US20070236259A1
公开(公告)日：2007-10-11
申请号：US11399848
申请日：2006-04-06
申请人： Johnny Chan , Philip Ng
发明人： Johnny Chan , Philip Ng
IPC分类号： H03K5/22
CPC分类号： H03K5/24
摘要： A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.
摘要翻译：用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

6. 发明申请

US20070121384A1 Method and apparatus for implementing walkout of device junctions 有权
标题翻译：用于实现设备路口迂回的方法和装置
公开(公告)号：US20070121384A1
公开(公告)日：2007-05-31
申请号：US11291498
申请日：2005-11-30
申请人： Philip Ng , Jinshu Son , Johnny Chan
发明人： Philip Ng , Jinshu Son , Johnny Chan
IPC分类号： G11C11/34
CPC分类号： G11C5/145 , G11C5/147
摘要： A high-voltage charge pump circuit includes a charge pump circuit. A first high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high-voltage output circuits to the output of the high-voltage charge pump circuit.
摘要翻译：高压电荷泵电路包括电荷泵电路。第一高压输出电路被配置为将电荷泵的输出电压设置为为常规编程而选择的第一电压电平并擦除存储器单元。第二高电压输出电路被配置为将电荷泵的输出电压设置为选择用于器件结的迂回的第二电压电平，第二电压电平高于第一电压电平。第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

7. 发明申请

US20070216397A1 Method of testing power-on reset circuit and receiving circuit resetting capability 有权
标题翻译：测试上电复位电路和接收电路复位能力的方法
公开(公告)号：US20070216397A1
公开(公告)日：2007-09-20
申请号：US11375838
申请日：2006-03-14
申请人： Johnny Chan , Philip Ng , James Hughes
发明人： Johnny Chan , Philip Ng , James Hughes
IPC分类号： G01R7/00
CPC分类号： G01R31/3181
摘要： A method of testing power-on reset circuitry in an integrated circuit comprises establishing the a first state of the integrated circuit that is different from a normal reset state of the circuit, lowering the VCC power supply voltage from a normal high operating level VH to a specified lower level VP then raising it back to the normal high level, then determining whether or not the integrated circuit has assumed the reset state. The testing can repeated with a plurality of lower VCC levels VP and under a variety of operating conditions to characterize resetting parameters and to designate pass/fail results for individual chips. If an AC voltage detector is part of the power-on reset circuitry, then it can tested separately, and DC testing occurs with very slow ramp rates for lowering and raising the power supply voltage.
摘要翻译：一种测试集成电路中的上电复位电路的方法包括建立与电路的正常复位状态不同的集成电路的第一状态，将VCC电源电压从正常的高工作电平V

8. 发明申请

US20070121382A1 Circuit to control voltage ramp rate 有权
标题翻译：电路控制电压斜坡率
公开(公告)号：US20070121382A1
公开(公告)日：2007-05-31
申请号：US11291606
申请日：2005-11-30
申请人： Johnny Chan , Philip Ng , Alan Renninger , Jinshu Son , Jeffrey Tsai , Tin-Wai Wong , Tsung-Ching Wu
发明人： Johnny Chan , Philip Ng , Alan Renninger , Jinshu Son , Jeffrey Tsai , Tin-Wai Wong , Tsung-Ching Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/12
摘要： A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.
摘要翻译：一种编程电路和方法，用于以增量的方式对受控或预定的电压脉冲施加电荷转移到非易失性存储单元的浮置栅极，或者从非易失性存储单元的浮动栅极流出，以控制栅极氧化物两端的整体电压。高于传输阈值电压的电压（例如高于隧道阈值电压）以逐步电荷转移方式施加到浮动栅极或从浮动栅极施加到低于薄氧化物损伤阈值的电压极限。控制整体电压可避免氧化物破坏，提高可靠性。

9. 发明申请

US20050140419A1 Circuit for auto-clamping input pins to a definite voltage during power-up or reset 有权
标题翻译：用于在上电或复位期间将输入引脚自动钳位到一定电压的电路
公开(公告)号：US20050140419A1
公开(公告)日：2005-06-30
申请号：US10749342
申请日：2003-12-31
申请人： Philip Ng , Jeff Tsai , Johnny Chan
发明人： Philip Ng , Jeff Tsai , Johnny Chan
IPC分类号： H03K17/22 , H03L5/00
CPC分类号： H03K17/223
摘要： An auto-grounding circuit responsive to a reset signal discharges an input terminal of an integrated circuit and its associated input line to ground, using a pull-down transistor coupled to the input line, with a gate of the pull-down transistor coupled to receive the reset signal. An exemplary circuit also includes a NAND gate and a second pull-down transistor to maintain an established voltage level of the input line after the reset signal is no longer asserted until the input terminal is driven by an applied input signal. The voltage maintaining circuitry is weaker than the main pull-down transistor to avoid interfering with normal operation of the input terminal.
摘要翻译：响应于复位信号的自动接地电路使用耦合到输入线的下拉晶体管将集成电路的输入端及其相关联的输入线放电到地，其中下拉式晶体管的栅极被耦合以接收复位信号。示例性电路还包括NAND门和第二下拉晶体管，以在复位信号不再被断言直到输入端被施加的输入信号驱动之前维持输入线的建立的电压电平。电压保持电路比主下拉晶体管弱，以避免干扰输入端子的正常工作。

10. 发明申请

US20050086440A1 Method and system for enhancing the endurance of memory cells 有权
标题翻译：提高记忆单元耐久性的方法和系统
公开(公告)号：US20050086440A1
公开(公告)日：2005-04-21
申请号：US10690082
申请日：2003-10-20
申请人： Johnny Chan , Philip Ng , Tinwai Wong
发明人： Johnny Chan , Philip Ng , Tinwai Wong
IPC分类号： G06F13/28 , G11C16/34 , H01L20060101
CPC分类号： G11C16/349
摘要： An integrated circuit device includes a plurality of non-volatile memory cells associated with a plurality of flag cells storing managing data. The managing data of the flag cells forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells to write new data and from which of the memory cells to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.
摘要翻译：集成电路装置包括与存储管理数据的多个标志单元相关联的多个非易失性存储单元。标志单元的管理数据形成数据集。该数据集用于确定多个存储器单元的哪个存储器单元写入新数据以及从哪个存储器单元读取当前存储的数据。每当将新值写入指定的存储器单元以指示要写入下一个的备用存储器单元和从下一个读取的备用存储器单元时，将数据组改变为不同的数据组。可以通过在数据集的每个连续变化中交替地将新值写入不同的标志单元来改变数据集。

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