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1. 发明授权

US08471595B1 Selectable dynamic/static latch with embedded logic 有权
标题翻译：具有嵌入式逻辑的可选动态/静态锁存器
公开(公告)号：US08471595B1
公开(公告)日：2013-06-25
申请号：US13353383
申请日：2012-01-19
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin , Michael R. Ouellette
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin , Michael R. Ouellette
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K3/35606 , G06F7/68 , H03K19/1737
摘要： A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
摘要翻译：可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。并联栅极和附加栅极的输出端连接到反馈回路。反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。

2. 发明申请

US20130093481A1 HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO 失效
标题翻译：高频CMOS可编程分频器，具有大的分辨率
公开(公告)号：US20130093481A1
公开(公告)日：2013-04-18
申请号：US13275367
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03L7/08
CPC分类号： H03L7/183 , H03K23/54
摘要： A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.
摘要翻译：锁相环（PLL）包括具有反馈分压器的PLL反馈电路。反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。该系列中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。最后的动态锁存器接收第四数据信号并输出第五数据信号。第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

3. 发明授权

US08525561B2 Phase lock loop having high frequency CMOS programmable divider with large divide ratio 失效
标题翻译：锁相环具有分频比大的高频CMOS可编程分频器
公开(公告)号：US08525561B2
公开(公告)日：2013-09-03
申请号：US13275367
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K21/00
CPC分类号： H03L7/183 , H03K23/54
摘要： A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.
摘要翻译：锁相环（PLL）包括具有反馈分压器的PLL反馈电路。反馈分压器具有第一动态锁存器，第一逻辑电路和多个串联连接的动态锁存器。每个串行连接的动态锁存器将附加的数据信号接收并串行连接到后续串行的动态锁存器。串联中的第二个到最后一个动态锁存器将第四个数据信号输出到该系列中的最后一个动态锁存器。最后的动态锁存器接收第四数据信号并输出第五数据信号。第一反馈回路从第二到最后动态锁存器接收第四数据信号，并从最后一个动态锁存器接收第五数据信号。第一反馈环路包括组合第四和第五数据信号的NAND电路，第一反馈环路输出第一反馈信号。

4. 发明申请

US20130093463A1 HIGH FREQUENCY CMOS PROGRAMMABLE DIVIDER WITH LARGE DIVIDE RATIO 有权
标题翻译：高频CMOS可编程分频器，具有大的分辨率
公开(公告)号：US20130093463A1
公开(公告)日：2013-04-18
申请号：US13275369
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K19/173
CPC分类号： H03K19/1737 , H03K19/17744
摘要： A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.
摘要翻译：动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。使用施加到两个输入的信号来执行四个逻辑运算。

5. 发明授权

US08791728B2 High frequency CMOS programmable divider with large divide ratio 有权
标题翻译：具有大分频比的高频CMOS可编程分频器
公开(公告)号：US08791728B2
公开(公告)日：2014-07-29
申请号：US13275369
申请日：2011-10-18
申请人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
发明人： John S. Austin , Kai D. Feng , Shiu Chung Ho , Zhenrong Jin
IPC分类号： H03K21/00
CPC分类号： H03K19/1737 , H03K19/17744
摘要： A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.
摘要翻译：动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。附加的通过门可操作地连接到第一锁存逻辑电路。一个附加的传递门控制更新的数据信号的通过。反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。使用施加到两个输入的信号来执行四个逻辑运算。

6. 发明申请

US20120266116A1 INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE 有权
标题翻译：集成的毫米波天线和基座上的收发器
公开(公告)号：US20120266116A1
公开(公告)日：2012-10-18
申请号：US13534350
申请日：2012-06-27
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器位于半导体衬底的前侧。通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。连接到收发器的天线位于位于基板正面的电介质层中。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

7. 发明授权

US08415999B2 High frequency quadrature PLL circuit and method 有权
公开(公告)号：US08415999B2
公开(公告)日：2013-04-09
申请号：US12845390
申请日：2010-07-28
申请人： Hanyi Ding , Kai D. Feng , Zhenrong Jin , Francis F. Szenher
发明人： Hanyi Ding , Kai D. Feng , Zhenrong Jin , Francis F. Szenher
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/22
摘要： A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.

8. 发明授权

US08232920B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US08232920B2
公开(公告)日：2012-07-31
申请号：US12187442
申请日：2008-08-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01Q1/38 , H01Q1/40
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器位于半导体衬底的前侧。通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。连接到收发器的天线位于位于基板正面的电介质层中。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

9. 发明授权

US08120110B2 Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US08120110B2
公开(公告)日：2012-02-21
申请号：US12188381
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

10. 发明申请

US20120025881A1 HIGH FREQUENCY QUADRATURE PLL CIRCUIT AND METHOD 有权
标题翻译：高频四极PLL电路及方法
公开(公告)号：US20120025881A1
公开(公告)日：2012-02-02
申请号：US12845390
申请日：2010-07-28
申请人： Hanyi Ding , Kai D. Feng , Zhenrong Jin , Francis F. Szenher
发明人： Hanyi Ding , Kai D. Feng , Zhenrong Jin , Francis F. Szenher
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/22
摘要： A method includes phase-shifting an output signal of a phase lock loop (PLL) circuit by applying an injection current to an output of a charge pump of a the PLL circuit. A circuit includes: a first phase lock loop (PLL) circuit and a second PLL circuit referenced to a same clock; a phase detector circuit that detects a phase difference between an output signal of the first PLL circuit and an output signal of the second PLL circuit; and an adjustable current source that applies an injection current to at least one of the first PLL circuit and the second PLL circuit based on an output of the phase detector circuit.
摘要翻译：一种方法包括通过向PLL电路的电荷泵的输出施加注入电流来相移锁相环（PLL）电路的输出信号。电路包括：第一锁相环（PLL）电路和参考相同时钟的第二PLL电路; 相位检测器电路，检测第一PLL电路的输出信号和第二PLL电路的输出信号之间的相位差; 以及可调电流源，其基于相位检测器电路的输出将注入电流施加到第一PLL电路和第二PLL电路中的至少一个。

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