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1. 发明授权

US07513160B2 Digital pulsed phase locked loop 失效
标题翻译：数字脉冲锁相环
公开(公告)号：US07513160B2
公开(公告)日：2009-04-07
申请号：US11806475
申请日：2007-05-31
申请人： John E. Lynch , David M. Blaker , David J. Colatosti
发明人： John E. Lynch , David M. Blaker , David J. Colatosti
IPC分类号： G01N29/04
CPC分类号： G01S15/003
摘要： A digital pulsed phase locked loop (DPPLL) provides exact measurements of echo phase, time, and/or position delay as well as echo amplitude. These exact measurements provide better and more reliable results that directly benefit the many real world applications for the DPPLL. The DPPLL permits simultaneous tracking of multiple echo pulses and considerably improved echo selection and sampling.
摘要翻译：数字脉冲锁相环（DPPLL）提供回波相位，时间和/或位置延迟以及回波幅度的精确测量。这些精确的测量提供更好和更可靠的结果，直接有益于DPPLL的许多现实世界的应用。 DPPLL允许同时跟踪多个回波脉冲，并显着改善回波选择和采样。

2. 发明授权

US5471500A Soft symbol decoding 失效
标题翻译：软符号解码
公开(公告)号：US5471500A
公开(公告)日：1995-11-28
申请号：US208156
申请日：1994-03-08
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
IPC分类号： H03M13/45 , H03M13/41 , H04L25/03 , H04L27/00 , H04L27/22 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41 , H03M13/4169 , H04L25/03318
摘要： There is disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric. When a hard decision bit is a zero, a preselected number of bits of a binary representation of the branch metric are concatenated with a hard decision bit to form the soft symbol. When the hard decision bit is a one, the ones complement of the preselected number of bits of the binary representation of the branch metric are concatenated with the hard decision bit to form the soft symbol. The concatenation function can be achieved using an exclusive OR function with the preselected bits of the binary representation of the branch metric and the hard decision bit to form the soft symbol. The hard decision bit may be selectable from more than one source.
摘要翻译：公开了用于从分支度量的二进制表示生成的解码过程中的软符号。当硬判决位为零时，分支度量的二进制表示的预先选择的位数与硬判决位连接以形成软符号。当硬判决位是一个时，分支度量的二进制表示的预先选择的比特数的一个补码与硬判决比特连接以形成软符号。可以使用具有分支度量的二进制表示的预选位的异或函数和硬判决位来形成级联功能以形成软符号。硬判决位可以从多个源选择。

3. 发明授权

US5425055A Digital radio modulator 失效
标题翻译：数字无线调制器
公开(公告)号：US5425055A
公开(公告)日：1995-06-13
申请号：US980541
申请日：1992-11-23
申请人： David M. Blaker
发明人： David M. Blaker
IPC分类号： H03M1/66 , H04B7/24 , H04L27/12 , H04L27/14 , H04L27/18 , H04L27/20 , H04L27/22
CPC分类号： H04L27/2092
摘要： A radio modulator/demodulator particularly suitable for TDMA mobile telephone use employs digital techniques for GMSK phase modulation. Phase numbers representative respectively of an intermediate frequency carrier and modulation symbols are combined digitally to combination phase numbers which are subjected to a single folded cosine table to produce a digital trignometric sequence of numbers for modulating the transmitter. Economy of components and memory is achieved and some of the modulator components are used in demodulation which is effected by the single look-up table used in sine and cosine mode alternately.
摘要翻译：特别适用于TDMA移动电话使用的无线电调制器/解调器使用用于GMSK相位调制的数字技术。分别代表中频载波和调制符号的相位数字数字地组合到经历单个折叠余弦表的组合相位数，以产生用于调制发射机的数字的数字轨迹序列。实现组件和存储器的经济性，并且一些调制器组件被用于由正弦和余弦模式中交替使用的单个查找表来实现的解调。

4. 发明授权

US08189591B2 Methods, systems and computer program products for packet ordering for parallel packet transform processing 失效
标题翻译：用于并行包变换处理的数据包排序的方法，系统和计算机程序产品
公开(公告)号：US08189591B2
公开(公告)日：2012-05-29
申请号：US09999647
申请日：2001-10-30
申请人： David M. Blaker , Raymond Savarda
发明人： David M. Blaker , Raymond Savarda
IPC分类号： H04L12/56
CPC分类号： H04L69/12 , H04L69/22
摘要： Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify the packets so as to identify related packets. A sequence identifier is assigned to the packets such that the sequence identifier identifies an ordering of the related packets. The processed packets are ordered based on the classification of the packets and the sequence identifier of the packets. Parallel packet transform processing may be particularly well suite to parallel cryptographic processing.
摘要翻译：处理数据包，同时保持数据包的顺序。接收到数据包和分配给数据包的序列标识符。序列标识符指定与分组相关联的串行顺序。分组被提供给多个并行分组变换处理器，并且使用分组变换处理器来处理分组。处理后的数据包根据报文的序列标识符进行排序。可以评估分组以对分组进行分类，以便识别相关分组。序列标识符被分配给分组，使得序列标识符识别相关分组的顺序。处理后的数据包根据数据包的分类和数据包的序列标识符进行排序。并行包转换处理可能特别适用于并行加密处理。

5. 发明授权

US06691143B2 Accelerated montgomery multiplication using plural multipliers 失效
标题翻译：使用多个乘数加速montgomery乘法
公开(公告)号：US06691143B2
公开(公告)日：2004-02-10
申请号：US09849667
申请日：2001-05-04
申请人： David M. Blaker
发明人： David M. Blaker
IPC分类号： G06F738
CPC分类号： G06F9/3879 , G06F7/728 , G06F21/123 , G06F21/72 , H04L9/0877 , H04L2209/125
摘要： Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output. An accumulator is configured to add the first vector multiplier output, and the second vector multiplier output, to produce a product output. The latency of Montgomery multiplication thereby can be reduced to nearly the latency of a single scalar multiplication.
摘要翻译：蒙哥马利乘数和方法将残差被乘数乘以残差乘数，使用标量乘法器，第一向量乘法器和第二向量乘法器来获得残差乘积。控制器被配置为使用乘法器的选定数字和矢量乘以模数和被乘数来控制标量乘法器，第一向量乘法器和第二向量乘数以重叠标量乘法。标量乘法器被配置为将乘法器的最低有效位乘以乘法器的第一选定位数，以产生标量乘法器输出。第一个向量乘数被配置为将标量乘法器输出乘以模数，以产生第一向量乘法器输出。第二向量乘法器被配置为将乘法器的第二选定位乘以乘法器，以产生第二向量乘法器输出。累加器被配置为添加第一向量乘法器输出和第二向量乘数输出以产生乘积输出。因此，Montgomery乘法的延迟可以减少到单个标量乘法的几乎等待时间。

6. 发明授权

US5465275A Efficient utilization of present state/next state registers 失效
标题翻译：高效利用当前状态/下一状态寄存器
公开(公告)号：US5465275A
公开(公告)日：1995-11-07
申请号：US153334
申请日：1993-11-16
申请人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
发明人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/45 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41
摘要： In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.
摘要翻译：根据本发明，一种用于在诸如通信系统或维特比解码器中确定下一状态累积成本的情况下有效利用存储器的技术。该系统包括具有分配给第一阵列的寄存器的一部分和分配给第二阵列的寄存器的一部分的存储器。该技术包括从第一阵列的存储寄存器检索当前状态累积成本，并基于当前状态累积成本计算下一状态累积成本。下一个状态累积成本被存储在第二阵列的存储寄存器中。第二个阵列被指定为包含当前状态累积成本。从第二阵列的存储寄存器检索当前状态累积成本，并用于计算后续的下一状态累积成本。随后的下一状态累积成本被存储在第一阵列的存储寄存器中。

7. 发明授权

US06820105B2 Accelerated montgomery exponentiation using plural multipliers 失效
标题翻译：使用多个乘数加速蒙哥马利乘数
公开(公告)号：US06820105B2
公开(公告)日：2004-11-16
申请号：US09849853
申请日：2001-05-04
申请人： David M. Blaker
发明人： David M. Blaker
IPC分类号： G06F772
CPC分类号： G06F9/3879 , G06F7/728 , G06F21/123 , G06F21/72 , H04L9/0877 , H04L2209/125
摘要： Montgomery exponentiators and methods modulo exponentiate a generator (g) to a power of an exponent (e). The Montgomery exponentiators and methods include a first multiplier that is configured to repeatedly square a residue of the generator, to produce a series of first multiplier output values at a first multiplier output. A second multiplier is configured to multiply selected ones of the series of first multiplier output values that correspond to a bit of the exponent that is binary one, by a partial result, to produce a series of second multiplier output values at a second multiplier output. By providing two multipliers that are serially coupled as described above, Montgomery exponentiation can be accelerated.
摘要翻译：蒙哥马利指数和方法将发电机（g）取幂为指数（e）的幂。蒙哥马利指数和方法包括第一乘法器，其被配置为重复地平方发生器的残差，以在第一乘法器输出处产生一系列第一乘法器输出值。第二乘法器被配置为通过部分结果将对应于二进制指数的比特的一系列第一乘法器输出值中的选定的乘法器乘以第二乘法器输出的一系列第二乘法器输出值。通过提供如上所述串联耦合的两个乘法器，可以加速蒙哥马利乘数。

8. 发明授权

US5490178A Power and time saving initial tracebacks 失效
标题翻译：功率和时间节省初始回溯
公开(公告)号：US5490178A
公开(公告)日：1996-02-06
申请号：US153333
申请日：1993-11-16
申请人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
发明人： David M. Blaker , Gregory S. Ellard , Mohammad S. Mobin
IPC分类号： H04L25/08 , H03M13/23 , H03M13/41 , H04L25/03 , H04L27/06 , H03M13/12
CPC分类号： H03M13/6331 , H03M13/3961 , H03M13/41 , H03M13/4169 , H03M13/6502 , H03M13/6569 , H04L25/03178
摘要： A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register. The second predetermined length is selected relative to the predetermined symbol instant to assure tracebacks do not cycle into branch origin data from a previous transmission burst. After all updates are complete, the update instruction is omitted and the traceback instruction repeatedly executed until all symbols from a transmission burst are decoded.
摘要翻译：公开了一种包括维特比解码器的数字通信系统，用于跟踪通过各种状态信息的网格和操作方法的路径。追溯确定解码的符号。分支原始数据的格架存储在寄存器阵列中。与符号时刻相关联的分支原始数据是一个单元。通过对协处理器执行数字信号处理（DSP）的更新指令来生成数据单元。将第一预定回溯长度写入回溯长度寄存器。第一预定回溯长度很小，以最小化从先前传输突发循环到分支原点数据的回溯。追溯由DSP提供协处理器启动单个追溯指令。维特比解码器在更新和追溯指令之间交替显示。在预定的符号时刻，通过重写追溯长度寄存器来将回溯长度增加到第二预定长度。相对于预定的符号时刻选择第二预定长度，以确保回溯不会从先前传输突发中循环到分支原点数据。所有更新完成后，省略更新指令，并重复执行回溯指令，直到来自传输突发的所有符号被解码。

9. 发明授权

US4581636A Scan conversion apparatus and method 失效
标题翻译：扫描转换装置和方法
公开(公告)号：US4581636A
公开(公告)日：1986-04-08
申请号：US596204
申请日：1984-04-02
申请人： David M. Blaker , Juin-Jet Hwang , Christopher P. Zobkiw
发明人： David M. Blaker , Juin-Jet Hwang , Christopher P. Zobkiw
IPC分类号： A61B8/14 , A61B8/00 , G01N29/04 , G01N29/26 , G01S7/298 , G01S7/52 , G01S7/531 , G01S7/539 , G01S7/62 , G01S15/89 , G06F17/17 , G06T11/00 , H04N7/01
CPC分类号： G06F17/175 , G01S15/8993 , G01S7/52044 , G01S7/52063 , G06T11/40
摘要： An improved scan converter for converting received echo signals representative of the amplitude of ultrasound energy returning from sampled points along a plurality of spaced apart paths distributed in an image space into signals to be displayed as display pixels in a raster scan display system. The scan converter includes a scan data memory for storing the received echo signals in quadrants of the scan data memory. Each quadrant is associated with even and odd numbered paths and sample row combinations. Sample rows are related to sample points along the spaced apart paths. The scan converter further includes a circuit for determining a gray scale value to be assigned to each selected display pixel based on a predetermined combination of four received echo signals adjacent the selected display pixel and chosen from the quadrants of the scan data memory. The improved scan converter is capable of operation in both linear and sector scan modes, and, when in the sector mode, over 90.degree. and 180.degree. sectors. Variable scaling between the image space and display space and correction of the hose error when the scanning system employs an oscillating wobbler scan head are provided. Various techniques for converting display pixel rectangular coordinates into polar coordinates in real time for raster scan display are employed.
摘要翻译：一种改进的扫描转换器，用于将表示从分布在图像空间中的多个间隔开的路径的采样点返回的超声能量的振幅的接收的回波信号转换成在光栅扫描显示系统中被显示为显示像素的信号。扫描转换器包括扫描数据存储器，用于将接收到的回波信号存储在扫描数据存储器的象限中。每个象限与偶数和奇数编号的路径和采样行组合相关联。样本行与沿间隔开的路径的采样点相关。扫描转换器还包括用于基于与所选择的显示像素相邻并从扫描数据存储器的象限中选择的四个接收到的回波信号的预定组合来确定要分配给每个选择的显示像素的灰度值的电路。改进的扫描转换器能够在线性和扇形扫描模式下工作，并且在扇区模式下，能够在90度和180度的扇区中运行。提供了扫描系统采用振荡摆动扫描头时，图像空间与显示空间之间的可变缩放以及软管错误的校正。采用用于光栅扫描显示实时地将显示像素直角坐标转换为极坐标的各种技术。

10. 发明授权

US6066096A Imaging probes and catheters for volumetric intraluminal ultrasound imaging and related systems 失效
标题翻译：用于体积管腔内超声成像和相关系统的成像探针和导管
公开(公告)号：US6066096A
公开(公告)日：2000-05-23
申请号：US74907
申请日：1998-05-08
申请人： Stephen W. Smith , Edward D. Light , Jason O. Fiering , David M. Blaker , Thomas A. Hruschka
发明人： Stephen W. Smith , Edward D. Light , Jason O. Fiering , David M. Blaker , Thomas A. Hruschka
IPC分类号： A61B5/042 , A61B8/08 , A61B8/12 , A61B19/00 , A61B8/00
CPC分类号： A61B8/12 , A61B8/4488 , A61B5/0422 , A61B8/0833 , A61B90/36 , Y10S128/916
摘要： A real time three dimensional ultrasound imaging probe apparatus is configured to be placed inside a body. The apparatus comprises an elongated body having proximal and distal ends with an ultrasonic transducer phased array connected to and positioned on the distal end of the elongated body. The ultrasonic transducer phased array is positioned to emit and receive ultrasonic energy for volumetric forward scanning from the distal end of the elongated body. The ultrasonic transducer phased array includes a plurality of sites occupied by ultrasonic transducer elements. At least one ultrasonic transducer element is absent from at least one of the sites, thereby defining an interstitial site. A tool is positioned at the interstitial site. In particular, the tool can be a fiber optic lead, a suction tool, a guide wire, an electrophysiological electrode, or an ablation electrode. Related systems are also discussed.
摘要翻译：实时三维超声成像探针装置被配置为放置在体内。该装置包括细长体，其具有近端和远端，超声换能器相控阵列连接到并定位在细长体的远端上。超声波换能器相控阵列被定位成从细长体的远端发射和接收用于体积向前扫描的超声波能量。超声波换能器相控阵列包括由超声换能器元件占据的多个位置。至少一个站点不存在至少一个超声波换能器元件，从而限定了间隙位置。工具位于插页式广告位置。特别地，该工具可以是光纤引线，吸引工具，导丝，电生理电极或消融电极。还讨论了相关系统。

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