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1. 发明申请

US20130320446A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20130320446A1
公开(公告)日：2013-12-05
申请号：US13576933
申请日：2012-07-18
申请人： Wei Wang , Jing Wang , Lei Guo
发明人： Wei Wang , Jing Wang , Lei Guo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/02521 , H01L21/0237 , H01L21/02488 , H01L29/045 , H01L29/7849 , H01L29/78603
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a rare earth oxide layer formed on the semiconductor substrate; a channel region formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region respectively, in which a relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：半导体衬底; 形成在半导体衬底上的稀土氧化物层; 形成在稀土氧化物层上的沟道区; 以及源极区域和漏极区域，分别形成在沟道区域的两侧，其中稀土氧化物层的晶格常数a与沟道区域的半导体材料的晶格常数b之间的关系和/或源极区和漏极区是a =（n±c）b，其中n是整数，c是晶格常数的失配比，0

2. 发明授权

US08546857B1 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08546857B1
公开(公告)日：2013-10-01
申请号：US13576937
申请日：2012-07-16
申请人： Jing Wang , Lei Guo , Wei Wang
发明人： Jing Wang , Lei Guo , Wei Wang
IPC分类号： H01L29/08 , H01L29/417 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/66636 , H01L29/7848
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a source region and a drain region defined in the semiconductor substrate respectively, and a trench formed in the source region and/or the drain region, in which a rare earth oxide layer is formed in the trench; a source and/or a drain formed on the rare earth oxide layer; and a channel region formed between the source and the drain. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the source and/or the drain and/or the channel region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：半导体衬底; 限定在半导体衬底中的源极区和漏极区，以及在沟道中形成有稀土氧化物层的源极区和/或漏极区中形成的沟槽; 在稀土氧化物层上形成的源极和/或漏极; 以及形成在源极和漏极之间的沟道区域。源极和/或漏极和/或沟道区的半导体材料的稀土氧化物层的晶格常数a与晶格常数b之间的关系为a =（n±c）b，其中n为整数，c是晶格常数的失配比，0

3. 发明申请

US20130240958A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20130240958A1
公开(公告)日：2013-09-19
申请号：US13521051
申请日：2012-05-29
申请人： Jing Wang , Lei Guo , Wei Wang
发明人： Jing Wang , Lei Guo , Wei Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76283 , H01L29/7846
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; an active region formed in the semiconductor substrate, in which the active region comprises: a channel region, and a source region and a drain region formed on both sides of the channel region respectively; and a first isolation trench formed in the semiconductor substrate and on both sides of the active region, in which a first rare earth oxide layer is formed in each first isolation trench to produce a stress in the channel region in a channel length direction.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：半导体衬底; 形成在所述半导体衬底中的有源区，其中所述有源区包括：沟道区，以及分别形成在所述沟道区两侧的源区和漏区; 以及形成在所述半导体衬底中并且在所述有源区的两侧上形成的第一隔离沟槽，其中在每个第一隔离沟槽中形成第一稀土氧化物层，以在沟道长度方向上的沟道区域中产生应力。

4. 发明申请

US20130320413A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20130320413A1
公开(公告)日：2013-12-05
申请号：US13576934
申请日：2012-07-18
申请人： Wei Wang , Jing Wang , Lei Guo
发明人： Wei Wang , Jing Wang , Lei Guo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78603 , H01L29/7849 , H01L29/78654 , H01L29/78681 , H01L29/78684
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a trench formed in the semiconductor substrate, in which a rare earth oxide layer is formed in the trench; a channel region partly or entirely formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region, respectively. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：半导体衬底; 形成在半导体衬底中的沟槽，其中在沟槽中形成稀土氧化物层; 部分或全部形成在稀土氧化物层上的沟道区; 以及分别形成在沟道区两侧的源区和漏区。稀土氧化物层的晶格常数a与沟道区域和/或源极区域和漏极区域的半导体材料的晶格常数b之间的关系为a =（n±c）b，其中n为整数，c是晶格常数的失配比，0

5. 发明申请

US20120025279A1 LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：低肖特基二极管半导体结构及其形成方法
公开(公告)号：US20120025279A1
公开(公告)日：2012-02-02
申请号：US13132760
申请日：2011-05-10
申请人： Jing Wang , Wei Wang , Lei Guo , Jun Xu
发明人： Jing Wang , Wei Wang , Lei Guo , Jun Xu
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/66636 , H01L29/0895 , H01L29/1054 , H01L29/41783 , H01L29/517 , H01L29/66477 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively.
摘要翻译：提供了一种低肖特基势垒半导体结构，包括：衬底; 在基板上形成具有低Ge含量的SiGe层; 在SiGe层上形成具有高Ge含量的沟道层; 形成在所述基板上的栅极叠层和形成在所述栅极堆叠的两侧上的一个或多个层的侧壁; 金属源和金属漏极分别形成在沟道层中和栅极堆叠的两侧; 以及分别形成在基板和金属源之间以及基板和金属引线之间的绝缘层。

6. 发明授权

US08860086B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08860086B2
公开(公告)日：2014-10-14
申请号：US13376765
申请日：2011-11-11
申请人： Jing Wang , Lei Guo
发明人： Jing Wang , Lei Guo
IPC分类号： H01L29/66 , H01L21/764 , H01L29/778 , H01L21/8234
CPC分类号： H01L29/778 , H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/66431
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a Si substrate (1100); a plurality of convex structures (1200) formed on the Si substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50 nm in width; a first semiconductor film (1300), in which the first semiconductor film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200); a buffer layer (2100) formed on the first semiconductor film (1300); and a high-mobility III-V compound semiconductor layer (2000) formed on the buffer layer (2100).
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：Si衬底（1100）; 形成在Si衬底（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案被空腔隔开，并且每两个相邻凸起结构（1200）之间的空腔是宽度小于50nm; 第一半导体膜（1300），其中第一半导体膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接; 形成在所述第一半导体膜（1300）上的缓冲层（2100）; 和形成在缓冲层（2100）上的高迁移率III-V族化合物半导体层（2000）。

7. 发明授权

US08704306B2 Strained Ge-on-insulator structure and method for forming the same 有权
标题翻译：应变绝缘体上的结构及其形成方法
公开(公告)号：US08704306B2
公开(公告)日：2014-04-22
申请号：US13263236
申请日：2011-08-25
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L27/12
CPC分类号： H01L29/78684 , H01L21/28255 , H01L29/165 , H01L29/7843 , H01L29/7846 , H01L29/7848
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer; and a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region, in which the source and the drain are a SixGe1-x:C source and a SixGe1-x:C drain respectively to produce a tensile strain in the channel region, in which x is within a range from 0 to 1 and a content of C is within a range from 0 to 7.5%. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅叠层; 以及形成在栅极堆叠下方的沟道区，以及形成在沟道区的侧面上的源极和漏极，源极和漏极分别为SixGe1-x：C源极和SixGe1-x：C沟道，以产生在通道区域中的拉伸应变，其中x在0至1的范围内，并且C的含量在0至7.5％的范围内。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

8. 发明授权

US08587029B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US08587029B2
公开(公告)日：2013-11-19
申请号：US13376429
申请日：2011-11-11
申请人： Jing Wang , Lei Guo
发明人： Jing Wang , Lei Guo
IPC分类号： H01L29/78
CPC分类号： H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823481
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate; a plurality of convex structures formed on the substrate, in which every two adjacent convex structures are separated by a cavity; a plurality of floated films, in which each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion is set between two adjacent sets of floated films; and a gate stack formed on each channel layer.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括基板; 形成在基板上的多个凸起结构，其中每两个相邻的凸起结构被空腔分开; 多个浮动膜，其中每个浮动膜形成在每两个相邻凸起结构之间并且与每两个相邻的凸起结构的顶部连接，浮动膜被分割成多个组，沟道层形成在每个组中的浮动膜之间的凸起结构，源极区和漏极区分别形成在沟道层的两侧上，并且隔离部分被设置在两个相邻的浮动膜组之间; 以及形成在每个沟道层上的栅极叠层。

9. 发明申请

US20130207161A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20130207161A1
公开(公告)日：2013-08-15
申请号：US13499661
申请日：2011-06-27
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/267 , H01L21/02
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for forming the same are provided. The semiconductor device comprises: a substrate (1); an insulating layer (2), formed on the substrate (1) and having a trench (21) to expose an upper surface of the substrate (1); a first buffer layer (3), formed on the substrate (1) and in the trench (21); and a compound semiconductor layer (4), formed on the first buffer layer (3), wherein an aspect ratio of the trench (21) is larger than 1 and smaller than 10, wherein the first buffer layer (3) is formed by a low-temperature reduced pressure chemical vapor deposition process at a temperature between 200° C. and 500° C., and wherein the compound semiconductor layer (4) is formed by a low-temperature metal organic chemical vapor deposition process at a temperature between 200° C. and 600° C.
摘要翻译：提供半导体器件及其形成方法。半导体器件包括：衬底（1）; 形成在所述基板（1）上并具有用于露出所述基板（1）的上表面的沟槽（21）的绝缘层（2）; 形成在所述基板（1）和所述沟槽（21）中的第一缓冲层（3）; 和形成在第一缓冲层（3）上的化合物半导体层（4），其中沟槽（21）的纵横比大于1且小于10，其中第一缓冲层（3）由在200℃至500℃之间的温度下进行低温减压化学气相沉积工艺，其中化合物半导体层（4）通过低温金属有机化学气相沉积工艺在200℃ ℃和600℃

10. 发明授权

US08440550B2 Method for forming strained layer with high Ge content on substrate and semiconductor structure 有权
标题翻译：在基板和半导体结构上形成具有高Ge含量的应变层的方法
公开(公告)号：US08440550B2
公开(公告)日：2013-05-14
申请号：US13126730
申请日：2010-11-29
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/78 , H01L21/20 , H01L21/265
CPC分类号： H01L21/76254 , H01L29/1054 , H01L29/78684 , H01L29/78687
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure may comprise a substrate (110); an insulation layer (120) formed on the substrate (110); a strained layer (130) formed on the insulation layer (120); a strained layer (140) with high Ge content formed on the strained layer (130); and a gate stack (160) formed on the strained layer (140) with high Ge content.
摘要翻译：提供半导体结构及其形成方法。半导体结构可以包括衬底（110）; 形成在所述基板（110）上的绝缘层（120）; 形成在绝缘层（120）上的应变层（130）; 在应变层（130）上形成具有高Ge含量的应变层（140）; 以及形成在具有高Ge含量的应变层（140）上的栅极堆叠（160）。

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