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1. 发明授权

US08530355B2 Mixed orientation semiconductor device and method 有权
标题翻译：混合取向半导体器件及方法
公开(公告)号：US08530355B2
公开(公告)日：2013-09-10
申请号：US11317737
申请日：2005-12-23
申请人： Jiang Yan , Danny Pak-Chum Shum , Armin Tilke
发明人： Jiang Yan , Danny Pak-Chum Shum , Armin Tilke
IPC分类号： H01L21/311
CPC分类号： H01L27/092 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
摘要翻译：制造半导体器件的方法从半导体晶片开始，半导体晶片包括覆盖第二半导体层的第一半导体层。在半导体晶片中蚀刻第一沟槽。第一个沟槽填充绝缘材料。在第一沟槽内蚀刻第二沟槽并穿过绝缘材料，使得绝缘材料沿着第一沟槽的侧壁保留。第二沟槽露出第二绝缘层的一部分。然后可以使用第二半导体层作为种子层在第二沟槽内生长半导体层。

2. 发明申请

US20090135655A1 Embedded Flash Memory Devices on SOI Substrates and Methods of Manufacture Thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US20090135655A1
公开(公告)日：2009-05-28
申请号：US12360985
申请日：2009-01-28
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： G11C11/34 , H01L21/77
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

3. 发明授权

US08031532B2 Methods of operating embedded flash memory devices 有权
标题翻译：操作嵌入式闪存设备的方法
公开(公告)号：US08031532B2
公开(公告)日：2011-10-04
申请号：US12709982
申请日：2010-02-22
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

4. 发明授权

US07687347B2 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US07687347B2
公开(公告)日：2010-03-30
申请号：US12360985
申请日：2009-01-28
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L21/336 , H01L21/82 , H01L21/00 , H01L21/84 , G11C7/00
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

5. 发明授权

US07495279B2 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US07495279B2
公开(公告)日：2009-02-24
申请号：US11223235
申请日：2005-09-09
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

6. 发明申请

US20100149882A1 Methods of Operating Embedded Flash Memory Devices 有权
标题翻译：操作嵌入式闪存设备的方法
公开(公告)号：US20100149882A1
公开(公告)日：2010-06-17
申请号：US12709982
申请日：2010-02-22
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： G11C16/04
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

7. 发明申请

US20100203703A1 Deep Trench Isolation Structures and Methods of Formation Thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US20100203703A1
公开(公告)日：2010-08-12
申请号：US12702368
申请日：2010-02-09
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L21/762
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

8. 发明授权

US07679130B2 Deep trench isolation structures and methods of formation thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US07679130B2
公开(公告)日：2010-03-16
申请号：US11367247
申请日：2006-03-03
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L27/115
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

9. 发明申请

US20060189045A1 Method for fabricating a sublithographic contact structure in a memory cell 审中-公开
标题翻译：在存储单元中制造亚光刻接触结构的方法
公开(公告)号：US20060189045A1
公开(公告)日：2006-08-24
申请号：US11331771
申请日：2006-01-13
申请人： Danny Pak-Chum Shum , Armin Tilke
发明人： Danny Pak-Chum Shum , Armin Tilke
IPC分类号： H01L21/339
CPC分类号： H01L45/1233 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , H01L21/76804 , H01L21/76816 , H01L45/06 , H01L45/126 , H01L45/1293 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： A method for fabricating a sublithographic contact structure in a memory cell in a semiconductor component is disclosed. In one embodiment, the method includes forming a trench structure having first spacers on walls of the trench structure, a first sublithographic dimension being formed in a region between the first spacers situated on mutually opposite walls in at least one direction parallel to a wafer surface. The insulator layer is etched in a region between the first spacers situated on mutually opposite walls for forming a first passage hole, the first spacers being used as an etching mask. A layer made of an electrically conductive material is deposited at least over the first passage hole and partially etching back the layer made of the electrically conductive material in the first passage hole forming a first contact electrode. A layer made of a resistance change material is deposited over the first passage hole and partially etching back the resistance change material in the first passage hole forming a resistance change material zone.
摘要翻译：公开了一种在半导体部件的存储单元中制造亚光刻接触结构的方法。在一个实施例中，该方法包括在沟槽结构的壁上形成具有第一间隔物的沟槽结构，第一亚光刻尺寸形成在平行于晶片表面的至少一个方向上位于相互相对的壁上的第一间隔件之间的区域中。在位于相互相对的壁上的第一间隔件之间的区域中蚀刻绝缘体层，以形成第一通孔，第一间隔件用作蚀刻掩模。由导电材料制成的层至少沉积在第一通孔上，并且在形成第一接触电极的第一通孔中部分地蚀刻由导电材料制成的层。由电阻变化材料制成的层沉积在第一通孔上，并且部分地蚀刻形成电阻变化材料区的第一通孔中的电阻变化材料。

10. 发明授权

US08258028B2 Deep trench isolation structures and methods of formation thereof 有权
标题翻译：深沟槽隔离结构及其形成方法
公开(公告)号：US08258028B2
公开(公告)日：2012-09-04
申请号：US12702368
申请日：2010-02-09
申请人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
发明人： Armin Tilke , Danny Pak-Chum Shum , Laura Pescini , Ronald Kakoschke , Karl Robert Strenz , Martin Stiftinger
IPC分类号： H01L21/763
CPC分类号： H01L27/11526 , H01L21/76224 , H01L27/105 , H01L27/11521 , H01L27/11546
摘要： Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要翻译：公开了深沟槽隔离结构及其形成方法。描述了用于增加形成在深沟槽隔离结构附近的寄生晶体管的阈值电压的几种方法和结构，包括将沟道阻挡区域注入深沟槽隔离结构的底表面，部分地填充深沟槽隔离的底部具有绝缘材料的结构，和/或用掺杂的多晶硅材料填充至少一部分深沟槽隔离结构。

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