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1. 发明申请

US20110212591A1 METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件晶体管的制造方法
公开(公告)号：US20110212591A1
公开(公告)日：2011-09-01
申请号：US12964562
申请日：2010-12-09
申请人： Jae-Geun OH , Young-Ho Lee , Jin-Ku Lee , Mi-Ri Lee
发明人： Jae-Geun OH , Young-Ho Lee , Jin-Ku Lee , Mi-Ri Lee
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/268 , H01L21/2686 , H01L21/28061 , H01L29/66575
摘要： A method for fabricating a transistor of a semiconductor device includes: forming a gate pattern over a substrate; forming a junction region by performing an on implantation process onto the substrate at opposite sides of the gate pattern; performing a solid phase epitaxial (SPE) process on the junction region at a temperature approximately ranging from 770° C. to 850° C.; and performing a rapid thermal annealing (RTA) process on the junction region.
摘要翻译：一种制造半导体器件的晶体管的方法包括：在衬底上形成栅极图案; 通过在所述栅极图案的相对侧上对所述衬底进行注入工艺来形成结区域; 在大约770℃至850℃的温度下在接合区域进行固相外延（SPE）工艺; 并在接合区域上进行快速热退火（RTA）处理。

2. 发明申请

US20110189843A1 PLASMA DOPING METHOD AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：等离子喷涂方法和使用其制造半导体器件的方法
公开(公告)号：US20110189843A1
公开(公告)日：2011-08-04
申请号：US12774311
申请日：2010-05-05
申请人： Jin-Ku Lee , Jae-Geun Oh , Young-Ho Lee , Mi-Ri Lee , Seung-Beom Baek
发明人： Jin-Ku Lee , Jae-Geun Oh , Young-Ho Lee , Mi-Ri Lee , Seung-Beom Baek
IPC分类号： H01L21/306
CPC分类号： H01L29/66575 , H01L21/306
摘要： A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.
摘要翻译：在三维（3D）导电结构的期望位置处形成掺杂区域的掺杂方法相对容易地控制掺杂深度和掺杂区域的掺杂剂量，具有浅掺杂深度，并且防止浮体效应。使用相同的掺杂方法制造半导体器件。该方法包括：形成具有侧壁的导电结构，暴露导电结构的侧壁的一部分，以及通过执行等离子体掺杂工艺在侧壁的暴露部分中形成掺杂区域。

3. 发明申请

US20110073940A1 SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有单面接触的半导体器件及其制造方法
公开(公告)号：US20110073940A1
公开(公告)日：2011-03-31
申请号：US12649999
申请日：2009-12-30
申请人： Jin-Ku LEE , Young-Ho Lee , Mi-Ri Lee
发明人： Jin-Ku LEE , Young-Ho Lee , Mi-Ri Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7845 , H01L21/28518 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/41791 , H01L29/42356 , H01L29/66666 , H01L29/7827 , H01L29/7856
摘要： A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second conductive layer over the first conductive layer, forming a plurality of active regions by etching the second conductive layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成掺杂有用于形成电池结的杂质的第一导电层，在第一导电层上形成第二导电层，通过蚀刻第二导电层形成多个有源区和所述第一导电层，所述多个有源区域通过沟槽彼此分开，形成连接到所述第一导电层的侧壁的侧面接触，以及形成多个金属位线，每个金属位线连接到所述侧面接触和填充每个沟槽的一部分。

4. 发明授权

US08349690B2 Semiconductor device with one-side-contact and method for fabricating the same 有权
公开(公告)号：US08349690B2
公开(公告)日：2013-01-08
申请号：US12649999
申请日：2009-12-30
申请人： Jin-Ku Lee , Young-Ho Lee , Mi-Ri Lee
发明人： Jin-Ku Lee , Young-Ho Lee , Mi-Ri Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/28518 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/41791 , H01L29/42356 , H01L29/66666 , H01L29/7827 , H01L29/7856
摘要： A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

5. 发明授权

US09117654B2 Methods of forming fine patterns in integrated circuit devices 有权
标题翻译：在集成电路器件中形成精细图案的方法
公开(公告)号：US09117654B2
公开(公告)日：2015-08-25
申请号：US13470773
申请日：2012-05-14
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L21/467 , H01L27/02 , H01L21/033 , H01L21/308 , H01L21/3213 , H01L21/762 , H01L23/544 , H01L27/115 , H01L27/105
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。间隔件形成在第一和第二掩模结构的相对侧壁上。第一掩模结构被选择性地从第一区域中的间隔物之间移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案在第二区域中。

6. 发明申请

US20140191405A1 METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案的方法
公开(公告)号：US20140191405A1
公开(公告)日：2014-07-10
申请号：US14208456
申请日：2014-03-13
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L23/528
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

7. 发明授权

US08318603B2 Method of forming patterns for semiconductor device 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US08318603B2
公开(公告)日：2012-11-27
申请号：US12653588
申请日：2009-12-16
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L21/311
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

8. 发明授权

US08057692B2 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US08057692B2
公开(公告)日：2011-11-15
申请号：US12290420
申请日：2008-10-30
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

9. 发明申请

US20100266094A1 DUAL-COOLED NUCLEAR FUEL ROD HAVING ANNULAR PLUGS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有环形管的双冷却核燃料棒及其制造方法
公开(公告)号：US20100266094A1
公开(公告)日：2010-10-21
申请号：US12559059
申请日：2009-09-14
申请人： Hyung-Kyu Kim , Jong-Hun Kim , Dae-Ho Kim , Kun-Woo Song , Kyung-Ho Yoon , Young-Ho Lee , Jae-Yong Kim , Kang-Hee Lee
发明人： Hyung-Kyu Kim , Jong-Hun Kim , Dae-Ho Kim , Kun-Woo Song , Kyung-Ho Yoon , Young-Ho Lee , Jae-Yong Kim , Kang-Hee Lee
IPC分类号： G21C3/16 , C21D1/40
CPC分类号： G21C3/02 , G21C3/10 , G21C21/02 , Y02E30/40
摘要： A dual-cooled nuclear fuel rod and a method of manufacturing the same are provided. The nuclear fuel rod includes an outer cladding tube having a circular cross section, an inner cladding tube having an outer diameter smaller than an inner diameter of the outer cladding tube, and a length longer than the outer cladding tube, and located in parallel in the outer cladding tube, a pellet charged in a space between the outer and inner cladding tubes and generating energy by nuclear fission, and first and second end plugs coupling opposite ends of the outer cladding tube to stepped outer joints formed on outer circumferences of first ends thereof and coupling opposite ends of the inner cladding tube to stepped inner joints formed on inner circumferences of the first ends thereof.
摘要翻译：提供了双冷核燃料棒及其制造方法。核燃料棒包括具有圆形横截面的外包层管，外包层的外径小于外包层管的内径，长度比外包层管长，并且平行于外包层管，填充在外包层管和内包壳管之间的空间中并通过核裂变产生能量的颗粒，以及将外包层管的相对端连接到形成在其第一端的外周上的阶梯式外接头的第一和第二端塞并且将内包层管的相对端连接到形成在其第一端的内周上的阶梯式内接头。

10. 发明申请

US20100221919A1 Method of forming patterns for semiconductor device 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20100221919A1
公开(公告)日：2010-09-02
申请号：US12653588
申请日：2009-12-16
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L21/302
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

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