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1. 发明授权

US5965913A Dense vertical programmable read only memory cell structures and processes for making them 失效
公开(公告)号：US5965913A
公开(公告)日：1999-10-12
申请号：US844002
申请日：1997-04-18
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/01 , H01L29/10 , H01L29/40
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

2. 发明授权

US5512505A Method of making dense vertical programmable read only memory cell structure 失效
标题翻译：制作密集垂直可编程只读存储单元结构的方法
公开(公告)号：US5512505A
公开(公告)日：1996-04-30
申请号：US423218
申请日：1995-04-17
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115 , Y10S148/05
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

3. 发明授权

US5847425A Dense vertical programmable read only memory cell structures and processes for making them 失效
公开(公告)号：US5847425A
公开(公告)日：1998-12-08
申请号：US341411
申请日：1994-11-17
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

4. 发明授权

US5380672A Dense vertical programmable read only memory cell structures and processes for making them 失效
标题翻译：密集的垂直可编程只读存储单元结构和制造它们的过程
公开(公告)号：US5380672A
公开(公告)日：1995-01-10
申请号：US117219
申请日：1993-09-03
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

5. 发明授权

US5343063A Dense vertical programmable read only memory cell structure and processes for making them 失效
标题翻译：密集的垂直可编程只读存储单元结构和制造它们的过程
公开(公告)号：US5343063A
公开(公告)日：1994-08-30
申请号：US629250
申请日：1990-12-18
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

6. 发明授权

US06954381B2 EEPROM with split gate source side injection with sidewall spacers 失效
标题翻译：具有分离栅源的EEPROM与侧壁间隔件的注入
公开(公告)号：US06954381B2
公开(公告)日：2005-10-11
申请号：US10225105
申请日：2002-08-20
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C7/00 , G11C16/00 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L31/107 , H01L33/00
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L29/7881
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一个写操作，并执行另一个验证操作。这一写/验证过程被重复，直到验证成功，如检测到或基本为零，位线电流。

7. 发明授权

US6002152A EEPROM with split gate source side injection with sidewall spacers 有权
标题翻译：具有分离栅源的EEPROM与侧壁间隔件的注入
公开(公告)号：US6002152A
公开(公告)日：1999-12-14
申请号：US207956
申请日：1998-12-09
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C11/56 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

8. 发明授权

US5883409A EEPROM with split gate source side injection 失效
公开(公告)号：US5883409A
公开(公告)日：1999-03-16
申请号：US908744
申请日：1997-08-07
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

9. 发明授权

US5910925A EEPROM with split gate source side injection 失效
标题翻译：带分流栅源的EEPROM注入
公开(公告)号：US5910925A
公开(公告)日：1999-06-08
申请号：US65409
申请日：1998-04-23
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： A novel memory structure in which memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.
摘要翻译：一种新颖的存储器结构，其中存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列形成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。

10. 发明授权

US5776810A Method for forming EEPROM with split gate source side injection 失效
标题翻译：用分离栅源侧注入形成EEPROM的方法
公开(公告)号：US5776810A
公开(公告)日：1998-07-07
申请号：US193707
申请日：1994-02-09
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , H01L27/115 , H01L29/42324 , H01L29/42328 , H01L29/7885 , G11C2211/5634
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

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