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1. 发明授权

US07948458B2 Amplifier circuit and display device 有权
标题翻译：放大器电路和显示装置
公开(公告)号：US07948458B2
公开(公告)日：2011-05-24
申请号：US11504312
申请日：2006-08-15
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0248 , G09G2310/027 , G09G2310/0291 , G09G2310/06 , G09G2320/0233
摘要： An amplifier circuit and display device utilizing the amplifier circuit are provided. The amplifier circuit comprises a buffer amplifier which stabilizes an input signal and outputs a stabilized output signal. By supplying to the input terminal of the buffer amplifier, a voltage derived by adding a difference between the input signal and the output signal to the input signal, it is possible to change the input signal level in accordance with the deviation of the buffer amplifier, which allows correction of the output level to a suitable level.
摘要翻译：提供了利用放大器电路的放大器电路和显示装置。放大器电路包括缓冲放大器，其稳定输入信号并输出稳定的输出信号。通过向缓冲放大器的输入端提供通过将输入信号和输出信号之间的差加到输入信号而导出的电压，可以根据缓冲放大器的偏差改变输入信号电平，这允许将输出电平校正到合适的电平。

2. 发明申请

US20060233007A1 Display 有权
标题翻译：显示
公开(公告)号：US20060233007A1
公开(公告)日：2006-10-19
申请号：US11392723
申请日：2006-03-30
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： G11C19/08
CPC分类号： G11C19/00 , G11C19/28
摘要： A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.
摘要翻译：获得能够禁止逻辑合成电路在无意定时将信号输出到栅极线或漏极线的显示器。在该显示中，至少第一移位寄存器电路部分或第二移位寄存器电路部分中的至少一个包括复位晶体管，用于将输出第一移位信号或第二移位信号的节点的电压源转换为第二电压源，响应于从其先前的移位寄存器电路部分接收到的相对于扫描方向至少两个级的输出信号，接通逻辑合成电路部分的晶体管。

3. 发明授权

US07692620B2 Display 有权
标题翻译：显示
公开(公告)号：US07692620B2
公开(公告)日：2010-04-06
申请号：US11387792
申请日：2006-03-24
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G11C19/00 , G11C19/28
摘要： A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.
摘要翻译：获得能够禁止逻辑合成电路在无意定时将信号输出到栅极线或漏极线的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括由多个第一导电型晶体管构成的逻辑合成电路部分，该多个第一导电型晶体管用于接收第一移位信号的第一电压源和第二移位信号，并通过逻辑合成输出移位输出信号第一移位信号和第二移位信号。至少第一移位寄存器电路部分或第二移位寄存器电路部分至少包括复位晶体管，用于将输出第一移位信号或第二移位信号的节点的电压源转换为不导通晶体管的第二电压源逻辑合成电路部分响应规定的驱动信号。

4. 发明授权

US07667682B2 Display 有权
标题翻译：显示
公开(公告)号：US07667682B2
公开(公告)日：2010-02-23
申请号：US11285212
申请日：2005-11-23
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G3/34 , G11C19/00
CPC分类号： G09G3/3688 , G09G3/3208 , G09G3/3266 , G09G3/3275 , G09G3/3677 , G09G2330/021 , G11C19/184 , G11C19/28
摘要： A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.
摘要翻译：提供了具有能够抑制功耗增加的移位寄存器电路的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括移位寄存器电路部分，该移位寄存器电路部分包括响应于第一信号而导通的第二晶体管的第一电路部分和响应于第二信号提供ON的第六晶体管导通的第二电路部分 - 与第二晶体管的导通状态周期不重叠的状态周期，以及用于分别切换提供给第二和第六晶体管的第一和第二信号的输入信号切换电路部分。

5. 发明申请

US20070040821A1 Amplifier circuit and display device 有权
标题翻译：放大器电路和显示装置
公开(公告)号：US20070040821A1
公开(公告)日：2007-02-22
申请号：US11504142
申请日：2006-08-15
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G3/3614 , G09G3/3696 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/0291
摘要： In a buffer amplifier which receives an input signal on a positive input terminal, has an output terminal connected to a negative input terminal, and outputs a stabilized output signal, a switch for connecting the positive input terminal and the output terminal is provided. By switching the switch ON, the output of the buffer amplifier is set close to the input.
摘要翻译：在接收正输入端子上的输入信号的缓冲放大器中，具有连接到负输入端子的输出端子，并且输出稳定的输出信号，提供用于连接正输入端子和输出端子的开关。通过将开关切换到ON，缓冲放大器的输出设置为接近输入。

6. 发明申请

US20060221043A1 Display 有权
标题翻译：显示
公开(公告)号：US20060221043A1
公开(公告)日：2006-10-05
申请号：US11387792
申请日：2006-03-24
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G11C19/00 , G11C19/28
摘要： A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. This display comprises a shift register circuit including a logic composition circuit portion constituted of a plurality of first conductive type transistors turned on with a first voltage supply source for receiving a first shift signal and a second shift signal and outputting a shift output signal by logically compositing the first shift signal and the second shift signal with each other. At least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting the first shift signal or the second shift signal to a second voltage supply source not turning on the transistors of the logic composition circuit portion in response to a prescribed drive signal.
摘要翻译：获得能够禁止逻辑合成电路在无意定时将信号输出到栅极线或漏极线的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括由多个第一导电型晶体管构成的逻辑合成电路部分，该多个第一导电型晶体管用于接收第一移位信号的第一电压源和第二移位信号，并通过逻辑合成输出移位输出信号第一移位信号和第二移位信号。至少第一移位寄存器电路部分或第二移位寄存器电路部分至少包括复位晶体管，用于将输出第一移位信号或第二移位信号的节点的电压源转换为不导通晶体管的第二电压源逻辑合成电路部分响应规定的驱动信号。

7. 发明授权

US07777711B2 Display 有权
标题翻译：显示
公开(公告)号：US07777711B2
公开(公告)日：2010-08-17
申请号：US11392723
申请日：2006-03-30
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G11C19/28
摘要： A display capable of inhibiting a logic composition circuit from outputting a signal to a gate line or a drain line at unintentional timing is obtained. In this display, at least either a first shift register circuit portion or a second shift register circuit portion includes a reset transistor for resetting the voltage supply source of a node outputting a first shift signal or a second shift signal to a second voltage supply source not turning on transistors of a logic composition circuit portion in response to an output signal received from a shift register circuit portion precedent thereto by at least two stages with respect to a scanning direction.
摘要翻译：获得能够禁止逻辑合成电路在无意定时将信号输出到栅极线或漏极线的显示器。在该显示中，至少第一移位寄存器电路部分或第二移位寄存器电路部分中的至少一个包括复位晶体管，用于将输出第一移位信号或第二移位信号的节点的电压源转换为第二电压源，响应于从其先前的移位寄存器电路部分接收到的相对于扫描方向至少两个级的输出信号，接通逻辑合成电路部分的晶体管。

8. 发明申请

US20070164805A1 Level shift circuit 有权
标题翻译：电平移位电路
公开(公告)号：US20070164805A1
公开(公告)日：2007-07-19
申请号：US11653523
申请日：2007-01-16
申请人： Hiroyuki Horibata , Michiru Senda
发明人： Hiroyuki Horibata , Michiru Senda
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A level shift circuit basically has a configuration connecting two CMOS inverter circuits in parallel, furnishes an input signal to a control terminal of the inverter circuit, obtains an output signal from an output terminal of the inverter circuit, and has a function for level shifting the voltage amplitude of the input signal to the voltage amplitude of the supply voltage of the inverter circuit. The signal that is input by the gate terminal of an n-channel transistor arranged in each of two current paths forming the level shift circuit is not a direct input signal but a signal that is supplied by adding an offset corresponding to the threshold of each n-channel transistor with respect to the voltage amplitude of the input signal via the input voltage converter circuit.
摘要翻译：电平移位电路基本上具有并联连接两个CMOS反相器电路的配置，将输入信号提供给逆变器电路的控制端，从逆变器电路的输出端获得输出信号，并且具有电平转换功能输入信号的电压幅度与逆变器电路的电源电压的电压幅值。布置在形成电平移位电路的两个电流路径中的每一个中的由n沟道晶体管的栅极端子输入的信号不是直接输入信号，而是通过将与每个n的阈值相对应的偏移相加而提供的信号通道晶体管相对于输入信号经由输入电压转换器电路的电压振幅。

9. 发明申请

US20060125766A1 Display 有权
标题翻译：显示
公开(公告)号：US20060125766A1
公开(公告)日：2006-06-15
申请号：US11285212
申请日：2005-11-23
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3208 , G09G3/3266 , G09G3/3275 , G09G3/3677 , G09G2330/021 , G11C19/184 , G11C19/28
摘要： A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.
摘要翻译：提供了具有能够抑制功耗增加的移位寄存器电路的显示器。该显示器包括移位寄存器电路，该移位寄存器电路包括移位寄存器电路部分，该移位寄存器电路部分包括响应于第一信号而导通的第二晶体管的第一电路部分和响应于第二信号提供ON的第六晶体管导通的第二电路部分 - 与第二晶体管的导通状态周期不重叠的状态周期，以及用于分别切换提供给第二和第六晶体管的第一和第二信号的输入信号切换电路部分。

10. 发明授权

US07675499B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07675499B2
公开(公告)日：2010-03-09
申请号：US11504142
申请日：2006-08-15
申请人： Michiru Senda , Hiroyuki Horibata
发明人： Michiru Senda , Hiroyuki Horibata
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G3/3614 , G09G3/3696 , G09G2310/0251 , G09G2310/0256 , G09G2310/027 , G09G2310/0291
摘要： In a display device with a buffer amplifier which receives an input signal on a positive input terminal, has an output terminal connected to a negative input terminal, and outputs a stabilized output signal, a switch for connecting the positive input terminal and the output terminal is provided. By switching the switch ON, the output of the buffer amplifier is set close to the input.
摘要翻译：在具有接收正输入端子上的输入信号的缓冲放大器的显示装置中，具有连接到负输入端子的输出端子，并且输出稳定的输出信号，用于连接正输入端子和输出端子的开关是提供。通过将开关切换到ON，缓冲放大器的输出设置为接近输入。

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