专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5960319A Fabrication method for a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5960319A
公开(公告)日：1999-09-28
申请号：US699410
申请日：1996-08-19
申请人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665 , Y10S257/90
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译：公开了一种半导体器件及其制造方法。在硅半导体衬底上形成氮化硅膜。然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。

2. 发明申请

US20050045962A1 Semiconductor device having junction depths for reducing short channel effect 审中-公开
标题翻译：具有用于降低短沟道效应的结深度的半导体器件
公开(公告)号：US20050045962A1
公开(公告)日：2005-03-03
申请号：US10421713
申请日：2003-04-24
申请人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/2658 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665 , H01L29/6659
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译：公开了一种半导体器件及其制造方法。在硅半导体衬底上形成氮化硅膜。然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。

3. 发明授权

US06720627B1 Semiconductor device having junction depths for reducing short channel effect 失效
标题翻译：具有用于降低短沟道效应的结深度的半导体器件
公开(公告)号：US06720627B1
公开(公告)日：2004-04-13
申请号：US09698097
申请日：2000-10-30
申请人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
IPC分类号： H01L31113
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译：公开了一种半导体器件及其制造方法。在硅半导体衬底上形成氮化硅膜。然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。

4. 发明授权

US06255702B1 Semiconductor device having junction depths for reducing short channel effect 有权
标题翻译：具有用于降低短沟道效应的结深度的半导体器件
公开(公告)号：US06255702B1
公开(公告)日：2001-07-03
申请号：US09274973
申请日：1999-03-23
申请人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Masayuki Nakano , Shigeki Hayashida , Seizou Kakimoto , Toshimasa Matsuoka
IPC分类号： H01L2978
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26526 , H01L21/28052 , H01L21/28518 , H01L21/823807 , H01L29/665 , Y10S257/90
摘要： A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.
摘要翻译：公开了一种半导体器件及其制造方法。在硅半导体衬底上形成氮化硅膜。然后将杂质离子注入到硅半导体衬底的所需区域中，使得氮化硅膜的氮原子和硅原子与杂质离子的引入一起并入到硅半导体衬底的表面中。硅半导体衬底具有混入其中的最小化的氧含量，并且在注入杂质离子时恢复由氮原子填充的晶体缺陷。制造的半导体器件没有栅极电极耗尽和结电流泄漏之间的折衷关系以及短沟道效应。

5. 发明授权

US06747316B2 Surface-channel metal-oxide semiconductor transistors, their complementary field-effect transistors and method of producing the same 失效
标题翻译：表面沟道金属氧化物半导体晶体管，它们的互补场效应晶体管及其制造方法
公开(公告)号：US06747316B2
公开(公告)日：2004-06-08
申请号：US08678394
申请日：1996-07-02
申请人： Toshimasa Matsuoka , Seizou Kakimoto , Shigeki Hayashida , Hiroshi Iwata
发明人： Toshimasa Matsuoka , Seizou Kakimoto , Shigeki Hayashida , Hiroshi Iwata
IPC分类号： H01L2976
CPC分类号： H01L21/28052 , H01L21/823814 , H01L21/823842 , H01L29/665 , H01L29/6659
摘要： A surface-channel MOS transistor comprising; a gate electrode formed on a semiconductor substrate with a gate dielectric film therebetween and source/drain regions formed in the semiconductor substrate wherein the gate electrode is formed at least a polysilicon layer of a thickness of 100 to 200 nm uniformly doped with an impurity and the source/drain regions contains the same impurity in self-alignment with the gate electrode.
摘要翻译：一种表面沟道MOS晶体管，包括：形成在半导体衬底上的栅极电极，其栅极电介质膜和在半导体衬底中形成的源极/漏极区，其中栅电极至少形成均匀掺杂有杂质的厚度为100至200nm的多晶硅层，源/漏区包含与栅电极自对准相同的杂质。

6. 发明授权

US06927463B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06927463B2
公开(公告)日：2005-08-09
申请号：US10439540
申请日：2003-05-15
申请人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
IPC分类号： H01L21/76 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/772 , H01L29/76
CPC分类号： H01L27/0928 , H01L21/82385 , H01L21/823892
摘要： A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.
摘要翻译：本发明的半导体器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的深阱区; 形成在深井区域中的多个第二导电类型的浅阱区; 分别形成在所述多个浅井区域中的所述第一导电类型的源极区域和漏极区域; 在所述源极区域和所述漏极区域之间形成的沟道区域; 形成在沟道区上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中所述栅电极与相应的一个浅阱区电连接，并且所述浅阱区与相邻的浅阱区电分离。

7. 发明授权

US06255704B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06255704B1
公开(公告)日：2001-07-03
申请号：US08881697
申请日：1997-06-24
申请人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L21/82385 , H01L21/823892
摘要： A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.
摘要翻译：本发明的半导体器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的深阱区; 形成在深井区域中的多个第二导电类型的浅阱区; 分别形成在所述多个浅井区域中的所述第一导电类型的源极区域和漏极区域; 在所述源极区域和所述漏极区域之间形成的沟道区域; 形成在沟道区上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中所述栅电极与相应的一个浅阱区域电连接，并且所述浅阱区域与相邻的浅阱区域电分离。

8. 发明授权

US06573577B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06573577B1
公开(公告)日：2003-06-03
申请号：US09496944
申请日：2000-02-03
申请人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L21/82385 , H01L21/823892
摘要： A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.
摘要翻译：本发明的半导体器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的深阱区; 形成在深井区域中的多个第二导电类型的浅阱区; 分别形成在所述多个浅井区域中的所述第一导电类型的源极区域和漏极区域; 在所述源极区域和所述漏极区域之间形成的沟道区域; 形成在沟道区上的栅极绝缘膜; 以及形成在所述栅极绝缘膜上的栅电极，其中所述栅电极与相应的一个浅阱区域电连接，并且所述浅阱区域与相邻的浅阱区域电分离。

9. 发明授权

US06288429B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06288429B1
公开(公告)日：2001-09-11
申请号：US09319517
申请日：1999-07-07
申请人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
发明人： Hiroshi Iwata , Seizou Kakimoto , Masayuki Nakano , Toshimasa Matsuoka
IPC分类号： H01L2976
CPC分类号： H01L29/1087 , H01L27/092 , H01L29/7832
摘要： A semiconductor device which materializes dynamic threshold operation, on the assumption of the application of a bulk semiconductor substrate. The semiconductor substrate has a first conductivity type well region (11), a source region (12) and a drain region (13) of second conductivity type are made in the vicinity of the surface of the first conductivity type of well region (11), a channel region (14) is provided between these regions (12 and 13), a gate insulating film (15) and a gate electrode (16) are stacked in order on the channel region (14), and the gate electrode (16) is connected to the well region (11) through the contact hole (not shown in the figure) of the gate insulating film (15). In this transistor, as compared with a conventional SOI substrate, the resistance of the well region (11) can be lowered to about one-tenth.
摘要翻译：在假设应用体半导体衬底的情况下实现动态阈值操作的半导体器件。半导体衬底具有第一导电类型阱区（11），在第一导电类型的阱区（11）的表面附近形成第二导电类型的源区（12）和漏区（13）在这些区域（12,13）之间设置沟道区域（14），栅极绝缘膜（15）和栅极电极（16）依次层叠在沟道区域（14）上，栅电极（16））通过栅极绝缘膜（15）的接触孔（图中未示出）连接到阱区（11）。在该晶体管中，与传统的SOI衬底相比，阱区（11）的电阻可以降低到约十分之一。

10. 发明授权

US5976918A Method of forming insulating film with few hydrogen atom inclusions 失效
标题翻译：形成几乎没有氢原子夹杂物的绝缘膜的方法
公开(公告)号：US5976918A
公开(公告)日：1999-11-02
申请号：US985633
申请日：1997-12-04
申请人： Toshimasa Matsuoka , Masayuki Nakano , Satoshi Morishita , Hiroshi Iwata , Seizo Kakimoto , Takashi Fukushima
发明人： Toshimasa Matsuoka , Masayuki Nakano , Satoshi Morishita , Hiroshi Iwata , Seizo Kakimoto , Takashi Fukushima
IPC分类号： H01L29/78 , H01L21/314 , H01L21/318 , H01L21/324 , H01L21/00 , H01L21/20
CPC分类号： H01L21/3145
摘要： In accordance with the development of the fineness of MOSFETs, a gate insulating film and a capacitor insulating film are required to have a smaller thickness and a higher film quality. Accordingly, the present invention is intended to provide a method for forming a high-quality insulating film while preventing hydrogen atoms which cause a leak current and an electron trap from entering the insulating film. The present method uses a gas of molecules containing at least nitrogen, the gas is a compound which includes no oxygen atom and has no bond of a nitrogen atom and a hydrogen atom (N--H) and generates monoatomic nitrogen when the gas dissociates.
摘要翻译：根据MOSFET的细度的发展，需要栅极绝缘膜和电容器绝缘膜具有更小的厚度和更高的膜质量。因此，本发明旨在提供一种形成高品质绝缘膜的方法，同时防止引起漏电流的氢原子和电子陷阱进入绝缘膜。本方法使用至少含有氮的分子气体，气体是不含氧原子的化合物，并且当气体解离时，不产生氮原子和氢原子（N-H）的键并产生单原子氮。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式