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1. 发明申请

US20090129879A1 TOOL HEAD, MACHINE TOOL AND BORING METHOD OF BORE OF CYLINDER BLOCK USING THE MACHINE TOOL 有权
标题翻译：工具头，机器工具和钻孔方法使用机床工具
公开(公告)号：US20090129879A1
公开(公告)日：2009-05-21
申请号：US12282737
申请日：2007-03-12
申请人： Hideki Sadaoka , Hiromi Oshima , Shinji Nogami , Minoru Suzuki , Makoto Ouchi , Masanori Kikuchi
发明人： Hideki Sadaoka , Hiromi Oshima , Shinji Nogami , Minoru Suzuki , Makoto Ouchi , Masanori Kikuchi
IPC分类号： B23B35/00 , B23B51/08
CPC分类号： B23P23/02 , B23B41/12 , B23D77/042 , B23Q1/4876 , B24B33/027 , B24B33/08 , B24B41/04 , Y10T29/5168 , Y10T29/5176 , Y10T408/03 , Y10T408/36 , Y10T408/375 , Y10T408/856
摘要： The spindle drive unit of a combined machine tool drives the spindle. The tip end of the spindle is provided with a boring tool and a tool head having a rough grinding stone and a finishing grinding stone. The spindle drive unit has a first support unit and a second support unit capable of receiving the spindle therethrough and supporting it rotatably, a linear motor and a column slide mechanism for moving the first and second support unit in the axis direction of the spindle, and a spindle motor for rotating the spindle.
摘要翻译：组合机床的主轴驱动单元驱动主轴。主轴的末端设置有钻孔工具和具有粗磨石和精磨磨石的工具头。主轴驱动单元具有第一支撑单元和第二支撑单元，该第一支撑单元和第二支撑单元能够容纳主轴并支撑其可转动;线性马达和列滑动机构，用于沿主轴的轴线方向移动第一和第二支撑单元，用于旋转主轴的主轴电机。

2. 发明授权

US08287214B2 Tool head, machine tool and boring method of bore of cylinder block using the machine tool 有权
标题翻译：使用机床的气缸体工具头，机床和钻孔方法
公开(公告)号：US08287214B2
公开(公告)日：2012-10-16
申请号：US12282737
申请日：2007-03-12
申请人： Hideki Sadaoka , Hiromi Oshima , Shinji Nogami , Minoru Suzuki , Makoto Ouchi , Masanori Kikuchi
发明人： Hideki Sadaoka , Hiromi Oshima , Shinji Nogami , Minoru Suzuki , Makoto Ouchi , Masanori Kikuchi
IPC分类号： B23B39/16
CPC分类号： B23P23/02 , B23B41/12 , B23D77/042 , B23Q1/4876 , B24B33/027 , B24B33/08 , B24B41/04 , Y10T29/5168 , Y10T29/5176 , Y10T408/03 , Y10T408/36 , Y10T408/375 , Y10T408/856
摘要： The spindle drive unit of a combined machine tool drives the spindle. The tip end of the spindle is provided with a boring tool and a tool head having a rough grinding stone and a finishing grinding stone. The spindle drive unit has a first support unit and a second support unit capable of receiving the spindle therethrough and supporting it rotatably, a linear motor and a column slide mechanism for moving the first and second support unit in the axis direction of the spindle, and a spindle motor for rotating the spindle.
摘要翻译：组合机床的主轴驱动单元驱动主轴。主轴的末端设置有钻孔工具和具有粗磨石和精磨磨石的工具头。主轴驱动单元具有第一支撑单元和第二支撑单元，该第一支撑单元和第二支撑单元能够容纳主轴并支撑其可转动;线性马达和列滑动机构，用于沿主轴的轴线方向移动第一和第二支撑单元，用于旋转主轴的主轴电机。

3. 发明授权

US5914964A Memory fail analysis device in semiconductor memory test system 失效
标题翻译：半导体存储器测试系统中的内存故障分析设备
公开(公告)号：US5914964A
公开(公告)日：1999-06-22
申请号：US765048
申请日：1997-05-09
申请人： Takashi Saito , Hiromi Oshima
发明人： Takashi Saito , Hiromi Oshima
IPC分类号： G01R31/28 , G01R31/3193 , G11C29/00 , G11C29/44 , G11C29/56 , G06F11/00
CPC分类号： G11C29/56 , G11C29/44 , G01R31/31935
摘要： A memory fail analysis device for a semiconductor test system is attained in which fail data of a plurality of bits is read out in parallel to count the overall fail bits in a short period of time. In a fail bit counting device in a fail memory for the semiconductor memory test system, a fail memory block 358 is provided which is recognized as a single memory when measuring the MUT while divided into M blocks to read the stored data in M bits parallel at the same time when counting the number of fail bits. Further, a fail counter 360 is provided which receives the M bit data and encodes the number of either high or low logic levels in the data into binary code data and counts the binary code data to accumulate the counted number.
摘要翻译： PCT No.PCT / JP96 / 02016 Sec。 371日期1997年5月9日 102（e）日期1997年5月9日PCT提交1996年7月19日PCT公布。出版物WO97 / 04328 日期1997年2月6日获得半导体测试系统的存储器故障分析装置，其中并行读出多个位的故障数据以在短时间内对整个故障位进行计数。在用于半导体存储器测试系统的故障存储器中的故障比特计数装置中，提供了一个故障存储器块358，其在测量MUT时被识别为单个存储器，同时被分成M个块，以M位并行地读取存储的数据同时计数故障位数。此外，提供了一个接收M位数据并将数据中的高或低逻辑电平的数目编码成二进制码数据并对二进制码数据进行计数以累计计数的故障计数器360。

4. 发明授权

US5757815A Semiconductor memory test system 失效
标题翻译：半导体存储器测试系统
公开(公告)号：US5757815A
公开(公告)日：1998-05-26
申请号：US667655
申请日：1996-06-21
申请人： Kazushige Shimogama , Hiromi Oshima
发明人： Kazushige Shimogama , Hiromi Oshima
IPC分类号： G01R31/28 , G01R31/3193 , G11C29/00 , G11C29/56 , G06F11/00
CPC分类号： G01R31/31935 , G11C29/56
摘要： A semiconductor test system facilitates failure analysis of memory devices by being able to switch one situation where expected data used for an address fail memory is the same as data showing charge/discharge states in the memory cells of a memory device under test and another situation where the expected data is the same as data showing the expected output data of the device under test. For doing this, the semiconductor test system includes a prohibit means 7 for prohibiting the output of the an area inversion memory 22 from transferring to later stages, and an exclusive OR gate 6 which receives an output of the prohibit means 7 at one input and an output of an exclusive OR gate 23 at another input. The exclusive OR gate 6 supplies a resulted output to an address fail memory 5.
摘要翻译：半导体测试系统通过能够切换用于地址故障存储器的期望数据与表示被测存储器件的存储器单元中的充电/放电状态的数据相同的情况来促进存储器件的故障分析，预期数据与显示被测设备的预期输出数据的数据相同。为此，半导体测试系统包括用于禁止区域反转存储器22的输出转移到后级的禁止装置7以及在一个输入端接收禁止装置7的输出的异或门6和在另一输入端输出异或门23。异或门6将结果输出提供给地址故障存储器5。

5. 发明授权

US06490700B1 Memory device testing apparatus and data selection circuit 失效
标题翻译：存储器件测试装置和数据选择电路
公开(公告)号：US06490700B1
公开(公告)日：2002-12-03
申请号：US09310173
申请日：1999-05-12
申请人： Hiromi Oshima , Koichi Adachi
发明人： Hiromi Oshima , Koichi Adachi
IPC分类号： G11C2900
CPC分类号： G11C29/56 , G01R31/31813 , G01R31/31926 , G01R31/3193 , G11C29/48
摘要： A memory device testing apparatus has a pattern generator, which generates all of the signals used for a packet signal in one cycle, a pin data selector, which generates the packet signal by selecting some of the signals generated by the pattern generator and outputting the selected signals a plurality of times, a memory device socket, which can write test data into the memory device and read test data from the memory device, and a comparator, which compares expectation value data with test data.
摘要翻译：存储器件测试装置具有模式发生器，其在一个周期中产生用于分组信号的所有信号，引脚数据选择器，其通过选择由模式发生器产生的一些信号来产生分组信号，并输出所选择的信号多次，存储器件插座，其可以将测试数据写入存储器件并从存储器件读取测试数据;以及比较器，其将期望值数据与测试数据进行比较。

6. 发明授权

US08981786B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08981786B2
公开(公告)日：2015-03-17
申请号：US13445937
申请日：2012-04-13
申请人： Hiromi Oshima
发明人： Hiromi Oshima
IPC分类号： G01R31/02 , G11C29/56 , G01R31/317
CPC分类号： G11C29/56012 , G01R31/31726
摘要： A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to a sampling clock corresponding to the clock signal output by the device under test or a timing of a timing signal corresponding to a test period of the test apparatus; a judging section that judges pass/fail of the device under test, based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value; and a designating section that designates whether the data acquiring section acquires the data signal at the timing corresponding to the sampling clock or at the timing corresponding to the timing signal.
摘要翻译：一种测试被测设备输出数据信号的测试装置和指示要对数据信号进行采样的定时的时钟信号，该测试装置包括：数据获取部分，其获取被测器件输出的数据信号; 在对应于由被测器件输出的时钟信号的采样时钟或对应于测试设备的测试周期的定时信号的定时相对应的定时; 基于由数据获取部获取的数据信号与预期值之间的比较的结果，判定部分判断被测设备的通过/失败; 以及指定部分，其指定数据获取部分在与采样时钟相对应的定时处或在对应于定时信号的定时获取数据信号。

7. 发明授权

US08898531B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08898531B2
公开(公告)日：2014-11-25
申请号：US13445928
申请日：2012-04-13
申请人： Hiromi Oshima
发明人： Hiromi Oshima
IPC分类号： G01R31/28 , G06F11/00 , G11C29/56
CPC分类号： G11C29/56012
摘要： Provided is a test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a masking section that masks the acquisition of data by the data acquiring section, while the device under test is not outputting the clock signal; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value.
摘要翻译：提供一种测试装置，测试被测器件输出数据信号和表示数据信号采样定时的时钟信号，该测试设备包括一个数据获取部分，该数据获取部分获取由该器件输出的数据信号在对应于被测器件输出的时钟信号的定时进行测试; 屏蔽部分，在被测器件不输出时钟信号的同时，对数据获取部分的数据采集进行掩蔽; 以及判断部，其基于由数据获取部获取的数据信号与预期值之间的比较结果来判定被测设备的通过/失败。

8. 发明授权

US08718123B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08718123B2
公开(公告)日：2014-05-06
申请号：US13445932
申请日：2012-04-13
申请人： Kazumichi Yoshiba , Hiromi Oshima
发明人： Kazumichi Yoshiba , Hiromi Oshima
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20 , G01R31/28 , G06F11/00
CPC分类号： G11C29/56012 , G11C29/028
摘要： A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.
摘要翻译：一种测试装置，用于测试被测器件交换数据信号和时钟信号，所述测试设备包括测试信号提供部分，该测试信号提供部分将被测器件作为测试信号提供数据信号和时钟信号; 数据获取部分，在与被测器件输出的时钟信号相对应的时刻获取被测器件输出的数据信号; 判断部，其基于由数据获取部获取的数据信号与预期值之间的比较的比较结果，判定被测设备的通过/失败; 以及调整部，当进行调整时，调整用于产生获取数据信号的定时的时钟信号的延迟量。

9. 发明授权

US06877118B2 Memory testing method and memory testing apparatus 失效
标题翻译：内存测试方法和内存测试仪器
公开(公告)号：US06877118B2
公开(公告)日：2005-04-05
申请号：US09844301
申请日：2001-04-27
申请人： Hiromi Oshima , Noboru Okino , Yasuhiro Kawata
发明人： Hiromi Oshima , Noboru Okino , Yasuhiro Kawata
IPC分类号： G01R31/28 , G06F11/22 , G06F12/16 , G11C16/06 , G11C29/00 , G11C29/44 , G11C29/56
CPC分类号： G11C29/56 , G11C29/82
摘要： A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.
摘要翻译：提供了可以在短时间内测试闪存的存储器测试方法和装置。在测试具有块功能的闪速存储器的情况下，在存储器测试方法和其中将预定逻辑值写入构成存储器的每个块的存储器单元的装置中，从存储器单元读出写入的逻辑值以进行比较具有期望值，并且当读出的逻辑值和期望值彼此不一致时，这样的存储单元是故障存储器单元，则判定当故障存储器的数量每个块中的单元达到预定数量，该块是坏块，并且该块的测试被停止。此外，作出判定，当相同地址线上的故障存储单元的数量达到预定数量时，这样的地址线是不好的地址线，并且在这样做的决定之后，对坏的存储器单元的测试地址线基本上不受影响。

10. 发明授权

US6158037A Memory tester 失效
标题翻译：记忆体测试仪
公开(公告)号：US6158037A
公开(公告)日：2000-12-05
申请号：US91606
申请日：1998-06-19
申请人： Hiromi Oshima
发明人： Hiromi Oshima
IPC分类号： G01R31/28 , G01R31/319 , G01R31/3193 , G11C29/04 , G11C29/10 , G11C29/44 , G11C29/56 , G06F11/00
CPC分类号： G01R31/31935 , G11C29/10 , G11C29/56 , G01R31/31926 , G11C29/44
摘要： There is provided a memory testing apparatus for testing an IC memory having a failure relief line or lines, which is constructed to sufficiently serve to test using a failure analysis memory having its storage capacity of two times that of a memory under test. An extended storage area having its storage capacity approximately equal to that of a memory under test MUT is provided in a failure analysis memory having a main storage area whose storage capacity is the same as that of the memory under test adjacent to one side of the main storage area in either one of the row address direction (X coordinate direction) or column address direction (Y address direction) thereof. In addition, an address converter is provided for converting an address signal for accessing the failure relief line or lines of the memory under test into an address signal for accessing the extended storage area to write position information of a failure memory cell or cells on the failure relief line or lines in the extended storage area of the failure analysis memory.
摘要翻译： PCT No.PCT / JP97 / 03851 Sec。 371日期：1998年6月19日 102（e）1998年6月19日PCT PCT 1997年10月23日PCT公布。第WO98 / 18133号公报日期：1998年4月30日提供了一种用于测试具有故障排除线或线路的IC存储器的存储器测试装置，其被构造为充分地用于使用具有其存储容量为存储容量的两倍的存储容量的故障分析存储器进行测试测试。具有与被测试存储器MUT的存储容量大致相同的存储容量的扩展存储区域被提供在故障分析存储器中，该故障分析存储器具有主存储区域，该主存储区域的存储容量与被测设备的一侧相邻的被测存储器的存储容量相同在存储区域的行地址方向（X坐标方向）或列地址方向（Y地址方向）中的任一方。另外，提供地址转换器，用于将用于访问故障排除线路的地址信号或被测试存储器的线路转换成用于访问扩展存储区域的地址信号，以写入故障存储器单元或故障单元的位置信息救生线或故障分析存储器扩展存储区域中的线路。

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