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1. 发明申请

US20220107782A1 FLOATING POINT MULTIPLY HARDWARE USING DECOMPOSED COMPONENT NUMBERS 有权
公开(公告)号：US20220107782A1
公开(公告)日：2022-04-07
申请号：US17506506
申请日：2021-10-20
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Anup Ramesh Kadkol , Ehsan Khish Ardestani Zadeh , Olivia Wu , Yuchen Hao , Thomas Mark Ulrich , Rakesh Komuravelli
IPC分类号： G06F7/487 , G06N3/02 , G06F17/16 , G06F7/485
摘要： A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.

2. 发明申请

US20210256363A1 MAPPING CONVOLUTION TO A CHANNEL CONVOLUTION ENGINE 有权
公开(公告)号：US20210256363A1
公开(公告)日：2021-08-19
申请号：US16793961
申请日：2020-02-18
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Rakesh Komuravelli , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
IPC分类号： G06N3/063 , G06N3/08 , G06F9/30 , G06F17/16
摘要： A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.

3. 发明申请

US20210049229A1 MAPPING CONVOLUTION TO A MATRIX PROCESSOR UNIT 有权
公开(公告)号：US20210049229A1
公开(公告)日：2021-02-18
申请号：US16543241
申请日：2019-08-16
申请人： Facebook, Inc.
发明人： Krishnakumar Nair , Abdulkadir Utku Diril , Dheevatsa Mudigere , Olivia Wu , Ehsan Khish Ardestani Zadeh , Yuchen Hao
IPC分类号： G06F17/15 , G06F17/16 , G06F9/30 , G06N20/00
摘要： A system comprises a matrix processor unit that includes a first type of register, a group of a second type of registers, and a plurality of calculation units. The first type of register is configured to concurrently store values from different rows of a first matrix. At least a portion of the first type of register is logically divided into groups of elements, and each of the groups corresponds to a different row of the first matrix. Each of the second type of registers is configured to concurrently store values from a plurality of different rows of a second matrix. Each of the calculation units corresponds to one of the second type of registers and is configured to at least in part determine a corresponding element in a result matrix of convoluting the second matrix with the first matrix.

4. 发明申请

US20210271451A1 MAPPING CONVOLUTION TO A PARTITION CHANNEL CONVOLUTION ENGINE 有权
公开(公告)号：US20210271451A1
公开(公告)日：2021-09-02
申请号：US16805339
申请日：2020-02-28
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Rakesh Komuravelli , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
IPC分类号： G06F7/544 , G06F17/15 , G06N20/00
摘要： A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.

5. 发明申请

US20210192359A1 SYSTEMS AND METHODS FOR REDUCING DATA MOVEMENT DURING CONVOLUTION OPERATIONS IN ARTIFICIAL NEURAL NETWORKS 有权
公开(公告)号：US20210192359A1
公开(公告)日：2021-06-24
申请号：US16722636
申请日：2019-12-20
申请人： Facebook, Inc.
发明人： Ehsan Khish Ardestani Zadeh , Martin Schatz , Krishnakumar Narayanan Nair , Yuchen Hao , Abdulkadir Utku Diril , Rakesh Komuravelli
IPC分类号： G06N3/10 , G06F17/15 , G06N3/04
摘要： The disclosed computer-implemented method may include (1) receiving, at a hardware accelerator that supports an ANN, an activation data set that is to undergo a convolution operation via a filter kernel of the ANN, (2) receiving, at the hardware accelerator, an argument indicating that the filter kernel exceeds at least one boundary of the activation data set when slid across a certain position during the convolution operation, (3) determining, based at least in part on the argument, that the hardware accelerator is to generate padding data at the boundary of the activation data set in connection with the certain position of the filter kernel, and then (4) performing, at the hardware accelerator, the convolution operation by processing a portion of the activation data set and the padding data when the filter kernel slides across the certain position. Various other systems and methods are also disclosed.

6. 发明授权

US11188303B2 Floating point multiply hardware using decomposed component numbers 有权
公开(公告)号：US11188303B2
公开(公告)日：2021-11-30
申请号：US16591042
申请日：2019-10-02
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Anup Ramesh Kadkol , Ehsan Khish Ardestani Zadeh , Olivia Wu , Yuchen Hao , Thomas Mark Ulrich , Rakesh Komuravelli
IPC分类号： G06F7/487 , G06F7/485 , G06F17/16 , G06N3/02
摘要： A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.

7. 发明申请

US20210124794A1 HIGH THROUGHPUT MATRIX PROCESSOR WITH SUPPORT FOR CONCURRENTLY PROCESSING MULTIPLE MATRICES 有权
公开(公告)号：US20210124794A1
公开(公告)日：2021-04-29
申请号：US16667791
申请日：2019-10-29
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Olivia Wu , Ehsan Khish Ardestani Zadeh , Abdulkadir Utku Diril , Thomas Mark Ulrich , Yuchen Hao , Rakesh Komuravelli , Aravind Kalaiah
IPC分类号： G06F17/16 , G06F7/544 , G06F17/15
摘要： A system comprises a data input vector unit, a weight input vector unit, and a plurality of calculation units of a matrix processor unit. The data input vector unit is configured to concurrently receive elements of different rows of a first and second data matrix. The weight input vector unit is configured to receive a combined weight vector and at least in part concurrently provide obtained weight elements of a first and second weight matrix to a corresponding first and second group of calculation units. Each calculation unit of the first and second group of calculation units is configured to multiply elements from the data input vector unit with elements of the corresponding weight matrix from the weight input vector unit and sum together multiplication results of the corresponding calculation unit to at least in part determine a corresponding element in a first or second convolution result matrix.

8. 发明申请

US20210349965A1 DEVICE AND METHOD FOR FLEXIBLY SUMMING MATRIX VALUES 有权
公开(公告)号：US20210349965A1
公开(公告)日：2021-11-11
申请号：US16869303
申请日：2020-05-07
申请人： Facebook, Inc.
发明人： Krishnakumar Narayanan Nair , Thomas Mark Ulrich , Ehsan Khish Ardestani Zadeh
IPC分类号： G06F17/16 , G06F7/78
摘要： A device (e.g., an application-specific integrated circuit chip) includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed, wherein: each element of the input matrix of elements is represented using a first number of bits, each value of a group of values stored in the input matrix is represented using a second number of bits greater than the first number of bits, and each value of the group of values is stored as split segments across more than one element of the elements of the input matrix. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.

9. 发明申请

US20210349690A1 USING A LOW-BIT-WIDTH DOT PRODUCT ENGINE TO SUM HIGH-BIT-WIDTH NUMBERS 有权
公开(公告)号：US20210349690A1
公开(公告)日：2021-11-11
申请号：US16869281
申请日：2020-05-07
申请人： Facebook, Inc.
发明人： Thomas Mark Ulrich , Krishnakumar Narayanan Nair , Ehsan Khish Ardestani Zadeh
IPC分类号： G06F7/544 , G06F7/483
摘要： A device (e.g., an integrated circuit chip) includes a dot product processing component, a data alignment component, and an accumulator. The dot product processing component is configured to calculate a dot product of a first group of elements stored in a first storage unit with a second group of elements, wherein: each element of the first group of elements is represented using a first number of bits, each value of a group of values stored in the first storage unit is represented using a second number of bits greater than the first number of bits, and each value of the group of values is stored as split segments across more than one element of the elements of the first group of elements. The data alignment component is configured to receive results of the dot product processing component and modify one or more of the results of the dot product processing component. The accumulator is configured to sum outputs of the data alignment component to at least in part determine a sum of the group of values.

10. 发明申请

US20210334072A1 MAPPING CONVOLUTION TO CONNECTED PROCESSING ELEMENTS USING DISTRIBUTED PIPELINED SEPARABLE CONVOLUTION OPERATIONS 有权
公开(公告)号：US20210334072A1
公开(公告)日：2021-10-28
申请号：US16855927
申请日：2020-04-22
申请人： Facebook, Inc.
发明人： Rakesh Komuravelli , Krishnakumar Narayanan Nair , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
IPC分类号： G06F7/544 , G06F7/50 , G06F7/523 , G06F17/16 , G06N3/08 , G06N20/00
摘要： A processor system comprises a plurality of dot product processor units and element-wise multiplication units. The dot product processor units perform a depthwise convolution of a data matrix with a separate depthwise convolution weight matrix for each data matrix channel. Each dot product processor unit performs at least a portion of the depthwise convolution for one or more data matrix channels. The element-wise multiplication units perform multiplication operations of a pointwise convolution. Each element-wise multiplication unit applies to each depthwise convolution partial result element received from one or more of the dot product processor units a corresponding data element from each of a plurality of pointwise convolution weight filters to determine element-wise multiplication unit results. The processor system sums together different groups of data elements from the element-wise multiplication unit results to at least in part calculate different data elements of a result of the pointwise convolution.

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