专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09147156B2 Apparatus and methods for synaptic update in a pulse-coded network 有权
标题翻译：脉冲编码网络中突触更新的装置和方法
公开(公告)号：US09147156B2
公开(公告)日：2015-09-29
申请号：US13239255
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran , Jeffrey Alexander Levin , Venkat Rangan , Erik Christopher Malone
发明人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran , Jeffrey Alexander Levin , Venkat Rangan , Erik Christopher Malone
IPC分类号： G06F1/16 , G06N3/04
CPC分类号： G06N3/049
摘要： Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.
摘要翻译：用于在诸如尖峰神经网络的网络中有效突触更新的装置和方法。在一个实施例中，响应于由突触后单元产生后突触脉冲的突触后更新被延迟，直到该单元接收到后续的突触前脉冲。先突触后更新是在突触后更新之后进行的，因此确保突触连接状态是最新的。延迟更新机制与系统“刷新”事件结合使用，以确保网络运行准确，防止各种突触前和突触后单位发射速率下的信息丢失。在一个变型中，网络分割机制用于网络处理设备，以便能够在有限的功能嵌入式硬件环境中处理网络信号。

2. 发明授权

US08719199B2 Systems and methods for providing a neural network having an elementary network description for efficient implementation of event-triggered plasticity rules 失效
标题翻译：用于提供具有用于有效实现事件触发可塑性规则的基本网络描述的神经网络的系统和方法
公开(公告)号：US08719199B2
公开(公告)日：2014-05-06
申请号：US13239163
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Filip Piekniewski , Jayram Moorkanikara Nageswaran
发明人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Filip Piekniewski , Jayram Moorkanikara Nageswaran
IPC分类号： G05B13/02 , G06N3/08
CPC分类号： G06N3/08 , G05B13/027 , G06N3/049 , G06N3/10
摘要： A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. The software and hardware engines are optimized to take into account short-term and long-term synaptic plasticity in the form of LTD, LTP, and STDP.
摘要翻译：公开了一种简单的格式，并被称为基本网络描述（END）。该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。软件和硬件引擎经过优化考虑了LTD，LTP和STDP形式的短期和长期突触可塑性。

3. 发明授权

US10210452B2 High level neuromorphic network description apparatus and methods 有权
公开(公告)号：US10210452B2
公开(公告)日：2019-02-19
申请号：US13385933
申请日：2012-03-15
申请人： Botond Szatmary , Eugene M. Izhikevich , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
发明人： Botond Szatmary , Eugene M. Izhikevich , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
IPC分类号： G06N3/10 , G06N3/04
摘要： Apparatus and methods for high-level neuromorphic network description (HLND) framework that may be configured to enable users to define neuromorphic network architectures using a unified and unambiguous representation that is both human-readable and machine-interpretable. The framework may be used to define nodes types, node-to-node connection types, instantiate node instances for different node types, and to generate instances of connection types between these nodes. To facilitate framework usage, the HLND format may provide the flexibility required by computational neuroscientists and, at the same time, provides a user-friendly interface for users with limited experience in modeling neurons. The HLND kernel may comprise an interface to Elementary Network Description (END) that is optimized for efficient representation of neuronal systems in hardware-independent manner and enables seamless translation of HLND model description into hardware instructions for execution by various processing modules.

4. 发明申请

US20130073499A1 APPARATUS AND METHOD FOR PARTIAL EVALUATION OF SYNAPTIC UPDATES BASED ON SYSTEM EVENTS 失效
标题翻译：基于系统事件部分评估更新的装置和方法
公开(公告)号：US20130073499A1
公开(公告)日：2013-03-21
申请号：US13239259
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
发明人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
IPC分类号： G06N3/04 , G06N3/06
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Apparatus and methods for partial evaluation of synaptic updates in neural networks. In one embodiment, a pre-synaptic unit is connected to a several post synaptic units via communication channels. Information related to a plurality of post-synaptic pulses generated by the post-synaptic units is stored by the network in response to a system event. Synaptic channel updates are performed by the network using the time intervals between a pre-synaptic pulse, which is being generated prior to the system event, and at least a portion of the plurality of the post synaptic pulses. The system event enables removal of the information related to the portion of the post-synaptic pulses from the storage device. A shared memory block within the storage device is used to store data related to post-synaptic pulses generated by different post-synaptic nodes. This configuration enables memory use optimization of post-synaptic units with different firing rates.
摘要翻译：用于部分评估神经网络中突触更新的装置和方法。在一个实施例中，突触前单元经由通信信道连接到几个后突触单元。与由突触后单元生成的多个突触后脉冲相关的信息由网络响应于系统事件存储。突触信道更新由网络使用在系统事件之前产生的预触觉脉冲与多个突触后脉冲的至少一部分之间的时间间隔来执行。系统事件使得能够从存储设备去除与突触后部分脉冲相关的信息。存储设备内的共享存储器块用于存储与由不同的突触后节点产生的突触后脉冲相关的数据。这种配置使得具有不同发射速率的突触后单元的存储器使用优化成为可能。

5. 发明授权

US09117176B2 Round-trip engineering apparatus and methods for neural networks 有权
标题翻译：神经网络的往返工程设备和方法
公开(公告)号：US09117176B2
公开(公告)日：2015-08-25
申请号：US13385937
申请日：2012-03-15
申请人： Botond Szatmary , Eugene M. Izhikevich , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
发明人： Botond Szatmary , Eugene M. Izhikevich , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
IPC分类号： G06N7/00 , G06N3/08 , G06N3/10 , G06F9/44
CPC分类号： G06N3/08 , G06F8/355 , G06N3/10
摘要： Apparatus and methods for high-level neuromorphic network description (HLND) framework that may be configured to enable users to define neuromorphic network architectures using a unified and unambiguous representation that is both human-readable and machine-interpretable. The framework may be used to define nodes types, node-to-node connection types, instantiate node instances for different node types, and to generate instances of connection types between these nodes. To facilitate framework usage, the HLND format may provide the flexibility required by computational neuroscientists and, at the same time, provides a user-friendly interface for users with limited experience in modeling neurons. The HLND kernel may comprise an interface to Elementary Network Description (END) that is optimized for efficient representation of neuronal systems in hardware-independent manner and enables seamless translation of HLND model description into hardware instructions for execution by various processing modules.
摘要翻译：用于高级神经形态网络描述（HLND）框架的装置和方法，其可以被配置为使得用户能够使用统一且明确的表示来定义神经形态网络架构，其是可读和机器可解释的。该框架可用于定义节点类型，节点到节点连接类型，不同节点类型的实例化节点实例，以及生成这些节点之间连接类型的实例。为了促进框架使用，HLND格式可以提供计算神经科学家所需的灵活性，并且同时为具有有限的神经元建模经验的用户提供用户友好的界面。 HLND内核可以包括到基本网络描述（END）的接口，其被优化用于以与硬件无关的方式有效地表示神经元系统，并且能够将HLND模型描述无缝地转换成硬件指令以供各种处理模块执行。

6. 发明授权

US08725662B2 Apparatus and method for partial evaluation of synaptic updates based on system events 失效
标题翻译：基于系统事件部分评估突触更新的装置和方法
公开(公告)号：US08725662B2
公开(公告)日：2014-05-13
申请号：US13239259
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
发明人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
IPC分类号： G06N3/08
CPC分类号： G06N3/049 , G06N3/063 , G06N3/08
摘要： Apparatus and methods for partial evaluation of synaptic updates in neural networks. In one embodiment, a pre-synaptic unit is connected to a several post synaptic units via communication channels. Information related to a plurality of post-synaptic pulses generated by the post-synaptic units is stored by the network in response to a system event. Synaptic channel updates are performed by the network using the time intervals between a pre-synaptic pulse, which is being generated prior to the system event, and at least a portion of the plurality of the post synaptic pulses. The system event enables removal of the information related to the portion of the post-synaptic pulses from the storage device. A shared memory block within the storage device is used to store data related to post-synaptic pulses generated by different post-synaptic nodes. This configuration enables memory use optimization of post-synaptic units with different firing rates.
摘要翻译：用于部分评估神经网络中突触更新的装置和方法。在一个实施例中，突触前单元经由通信信道连接到几个后突触单元。与由突触后单元生成的多个突触后脉冲相关的信息由网络响应于系统事件存储。突触信道更新由网络使用在系统事件之前产生的预触觉脉冲与多个突触后脉冲的至少一部分之间的时间间隔来执行。系统事件使得能够从存储设备去除与突触后部分脉冲相关的信息。存储设备内的共享存储器块用于存储与由不同的突触后节点产生的突触后脉冲相关的数据。这种配置使得具有不同发射速率的突触后单元的存储器使用优化成为可能。

7. 发明申请

US20130073492A1 ELEMENTARY NETWORK DESCRIPTION FOR EFFICIENT IMPLEMENTATION OF EVENT-TRIGGERED PLASTICITY RULES IN NEUROMORPHIC SYSTEMS 失效
标题翻译：有效实施神经系统中事件触发的塑性规则的基本网络描述
公开(公告)号：US20130073492A1
公开(公告)日：2013-03-21
申请号：US13239163
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Filip Piekniewski , Jayram Moorkanikara Nageswaran
发明人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Filip Piekniewski , Jayram Moorkanikara Nageswaran
IPC分类号： G05B13/02
CPC分类号： G06N3/08 , G05B13/027 , G06N3/049 , G06N3/10
摘要： A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. The software and hardware engines are optimized to take into account short-term and long-term synaptic plasticity in the form of LTD, LTP, and STDP.
摘要翻译：公开了一种简单的格式，并被称为基本网络描述（END）。该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。软件和硬件引擎经过优化考虑了LTD，LTP和STDP形式的短期和长期突触可塑性。

8. 发明授权

US09104973B2 Elementary network description for neuromorphic systems with plurality of doublets wherein doublet events rules are executed in parallel 有权
标题翻译：具有多个双重的神经形态系统的基本网络描述，其中并行执行双重事件规则
公开(公告)号：US09104973B2
公开(公告)日：2015-08-11
申请号：US13239123
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
发明人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
IPC分类号： G06N3/04 , G06N3/063 , G06N99/00
CPC分类号： G06N3/049 , G06N3/0454 , G06N3/063 , G06N99/007
摘要： A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.
摘要翻译：公开了一种简单的格式，并被称为基本网络描述（END）。该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。用于操作神经元网络的神经元网络和方法包括多个单元，其中每个单元具有存储器和多个双重元件，每个双引脚连接到一对多个单元。多个单元的单元更新规则的执行是与订单无关的，并且用于多个双工的双重事件规则的执行是与订单无关的。

9. 发明申请

US20130073495A1 ELEMENTARY NETWORK DESCRIPTION FOR NEUROMORPHIC SYSTEMS 有权
标题翻译：神经系统的基本网络描述
公开(公告)号：US20130073495A1
公开(公告)日：2013-03-21
申请号：US13239123
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
发明人： Eugene M. Izhikevich , Botond Szatmary , Csaba Petre , Jayram Moorkanikara Nageswaran , Filip Piekniewski
IPC分类号： G06N3/08 , G06N3/04
CPC分类号： G06N3/049 , G06N3/0454 , G06N3/063 , G06N99/007
摘要： A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.
摘要翻译：公开了一种简单的格式，并被称为基本网络描述（END）。该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。用于操作神经元网络的神经元网络和方法包括多个单元，其中每个单元具有存储器和多个双重元件，每个双引脚连接到一对多个单元。多个单元的单元更新规则的执行是与订单无关的，并且用于多个双工的双重事件规则的执行是与订单无关的。

10. 发明申请

US20130073491A1 APPARATUS AND METHODS FOR SYNAPTIC UPDATE IN A PULSE-CODED NETWORK 有权
标题翻译：用于脉冲编码网络中的快速更新的装置和方法
公开(公告)号：US20130073491A1
公开(公告)日：2013-03-21
申请号：US13239255
申请日：2011-09-21
申请人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
发明人： Eugene M. Izhikevich , Filip Piekniewski , Jayram Moorkanikara Nageswaran
IPC分类号： G06N3/02
CPC分类号： G06N3/049
摘要： Apparatus and methods for efficient synaptic update in a network such as a spiking neural network. In one embodiment, the post-synaptic updates, in response to generation of a post-synaptic pulse by a post-synaptic unit, are delayed until a subsequent pre-synaptic pulse is received by the unit. Pre-synaptic updates are performed first following by the post-synaptic update, thus ensuring synaptic connection status is up-to-date. The delay update mechanism is used in conjunction with system “flush” events in order to ensure accurate network operation, and prevent loss of information under a variety of pre-synaptic and post-synaptic unit firing rates. A large network partition mechanism is used in one variant with network processing apparatus in order to enable processing of network signals in a limited functionality embedded hardware environment.
摘要翻译：用于在诸如尖峰神经网络的网络中有效突触更新的装置和方法。在一个实施例中，响应于由突触后单元产生后突触脉冲的突触后更新被延迟，直到该单元接收到后续的突触前脉冲。先突触后更新是在突触后更新之后进行的，因此确保突触连接状态是最新的。延迟更新机制与系统刷新事件结合使用，以确保准确的网络运行，并防止各种突触前和突触后单位发射速率下的信息丢失。在一个变型中，网络分割机制用于网络处理设备，以便能够在有限的功能嵌入式硬件环境中处理网络信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式