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    • 1. 发明授权
    • High dynamic range digital fluxgate magnetometer
    • 高动态范围数字磁通门磁强计
    • US5939881A
    • 1999-08-17
    • US968597
    • 1997-11-13
    • Eric K. SlaterKirk K. Kohnen
    • Eric K. SlaterKirk K. Kohnen
    • G01R33/04H03M3/02H03M1/12
    • G01R33/04H03M3/43H03M3/456H03M3/458
    • An improved digital fluxgate magnetometer that uses digital logic and a high resolution digital to analog converter to digitize a magnetic signal for use by signal processing algorithms. The magnetometer includes an oscillator that outputs an oscillator signal and a magnetic fluxgate sensor having a drive coil coupled to the oscillator, a feedback coil, and a sense coil. An analog multiplier is coupled to the sense coil and the oscillator and outputs a signal to an analog low pass filter. A comparator is coupled to the analog multiplier, and a register is coupled to the comparator and outputs a logical 1 or a logical 0 in accordance with the output of the comparator. A digital filter receives the output of the register and produces a digital output of the digital fluxgate magnetometer. A high resolution digital to analog converter is coupled between the register and the feedback coil of the magnetic fluxgate sensor in a feedback loop of the sensor. The digital to analog converter produces a very high resolution digitized output (typically >22 bits) that is necessary to adequately represent the dynamic range of the sensor.
    • 一种改进的数字磁通门磁强计,其使用数字逻辑和高分辨率数模转换器来数字化磁信号以供信号处理算法使用。 磁力计包括输出振荡器信号的振荡器和具有耦合到振荡器的驱动线圈,反馈线圈和感测线圈的磁通门传感器。 模拟乘法器耦合到感测线圈和振荡器,并将信号输出到模拟低通滤波器。 比较器耦合到模拟乘法器,并且寄存器耦合到比较器并根据比较器的输出输出逻辑1或逻辑0。 数字滤波器接收寄存器的输出并产生数字磁通门磁力计的数字输出。 在传感器的反馈回路中,高分辨率数模转换器耦合在寄存器和磁通门传感器的反馈线圈之间。 数模转换器产生非常高分辨率的数字输出(通常> 22位),这足以表示传感器的动态范围。
    • 4. 发明授权
    • High resolution, high dynamic range analog-to-digital converter system and related techniques
    • 高分辨率,高动态范围的模数转换器系统及相关技术
    • US06784820B1
    • 2004-08-31
    • US10409844
    • 2003-04-09
    • James William CasalegnoFrank Philip MonteEric Kent SlaterKirk K. Kohnen
    • James William CasalegnoFrank Philip MonteEric Kent SlaterKirk K. Kohnen
    • H03M112
    • H03M1/181
    • An analog-to-digital converter system for sampling an input signal includes at least one offset channel. Each channel includes a differential amplifier with a signal input coupled to the input signal, an offset input for receiving an offset signal and an amplified difference output, an analog-to-digital converter having a signal input coupled to the amplified difference output and having a signal output, and an offset index signal source coupled to the differential amplifier offset input. The system further includes an offset controller having at least one output coupled to a corresponding at least one offset index signal source and at least one input coupled to a corresponding at least one analog-to-digital converter signal output. The system also includes a signal constructor having at least one input coupled to a corresponding at least one analog-to-digital converter signal output and operable to provide a relatively high resolution digital output signal.
    • 用于对输入信号进行采样的模拟 - 数字转换器系统包括至少一个偏移通道。 每个通道包括具有耦合到输入信号的信号输入的差分放大器,用于接收偏移信号和放大的差分输出的偏移输入,具有耦合到放大的差分输出的信号输入的模数转换器, 信号输出和耦合到差分放大器偏移输入的偏移索引信号源。 该系统还包括偏移控制器,其具有耦合到对应的至少一个偏移索引信号源的至少一个输出和耦合到对应的至少一个模数转换器信号输出的至少一个输入。 该系统还包括信号构造器,其具有耦合到对应的至少一个模数转换器信号输出的至少一个输入并且可操作以提供相对高分辨率的数字输出信号。
    • 6. 发明授权
    • High speed configurable cryptographic architecture
    • 高速可配置加密架构
    • US08050401B2
    • 2011-11-01
    • US11235842
    • 2005-09-27
    • Kirk K. Kohnen
    • Kirk K. Kohnen
    • H04L9/14
    • H04L9/0631H04L2209/24
    • Method and system to encrypt and decrypt data is provided. The method comprising, providing input data to be encrypted, said input data made up of a plurality of sub-data, each said sub-data comprising sequence of bits of data; dynamically selecting a plurality of invertible encryption parameters; and performing one or more rounds of a combination of data modification, sequence modification and data-sequence modification using plurality of selected encryption parameters deriving encrypted data. The system includes a processor for executing code for dynamically selecting a plurality of invertible encryption parameters.
    • 提供了加密和解密数据的方法和系统。 该方法包括:提供要加密的输入数据,由多个子数据构成的所述输入数据,每个所述子数据包括数据位序列; 动态地选择多个可逆加密参数; 以及使用导出加密数据的多个所选择的加密参数来执行数据修改,序列修改和数据序列修改的组合的一轮或多轮。 该系统包括用于执行用于动态选择多个可逆加密参数的代码的处理器。
    • 7. 发明授权
    • Magnetic dipole target classifier and method
    • 磁偶极子目标分类器及方法
    • US5831873A
    • 1998-11-03
    • US789032
    • 1997-01-27
    • Kirk K. KohnenHarold C. GilbertWilbur W. Eaton, Jr.
    • Kirk K. KohnenHarold C. GilbertWilbur W. Eaton, Jr.
    • G01V3/08G01R33/12
    • G01V3/08
    • A target's magnetic dipole includes both a permanent component and an induced component that is caused by the interaction of the target at a given heading with the ambient magnetic field. In order to accurately classify targets, a library of characterization matrices is built for a plurality of candidate targets. The matrices characterize what the magnetic dipoles would be in a given ambient magnetic field at a particular heading. In practice, some localization algorithm is used to provide a target's magnetic dipole and heading. Magnetic dipoles for each of the candidate targets are predicted using the target's heading, the ambient magnetic field, and the characterization matrices. The target is then classified as the candidate target(s) providing the best match to the target's measured magnetic dipole.
    • 目标的磁偶极子包括由给定航向的目标与环境磁场的相互作用引起的永久分量和诱发分量。 为了准确地对目标进行分类,为多个候选目标构建了表征矩阵库。 矩阵表征在特定航向的给定环境磁场中磁偶极子将是什么。 在实践中,使用一些定位算法来提供目标的磁偶极子和航向。 使用目标的航向,环境磁场和表征矩阵预测每个候选目标的磁偶极子。 然后将目标分类为与目标的测量磁偶极子最佳匹配的候选目标。
    • 8. 发明授权
    • Method of logic gate reduction in a logic gate array
    • 逻辑门阵列中逻辑门还原的方法
    • US5189629A
    • 1993-02-23
    • US533985
    • 1990-06-06
    • Kirk K. Kohnen
    • Kirk K. Kohnen
    • G06F17/50
    • G06F17/505
    • A method of gate reduction in a gate width limited logic array. Common sub-groups of inputs associated with an array output are collected. Logical functions are then reimplemented, using the common subgroups implemented as single gates resulting in an implementation of the logical functions that uses few active devices. The method uses a constraint typically placed on gate array logic that gates wider than four inputs cannot be used. The method is applicable to combinatorial digital logic devices only. The method of the present invention is applicable to large scale integration (LSI) and very large scale integration (VLSI) integrated circuit devices.
    • 栅极宽度限制逻辑阵列中栅极还原的方法。 收集与阵列输出相关联的输入的公共子组。 然后使用实现为单个门的公共子组重新实现逻辑功能,从而实现使用少量有效设备的逻辑功能。 该方法使用通常放置在栅极阵列逻辑上的约束,不能使用比四个输入更宽的栅极。 该方法仅适用于组合数字逻辑器件。 本发明的方法适用于大规模集成(LSI)和大规模集成(VLSI)集成电路器件。