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1. 发明申请

US20140315366A1 Semiconductor Device and Method of Making 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US20140315366A1
公开(公告)日：2014-10-23
申请号：US13704615
申请日：2012-12-14
申请人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
发明人： Dongping Wu , Chenyu Wen , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L29/66 , H01L21/768 , H01L21/283
CPC分类号： H01L29/665 , H01L21/283 , H01L21/28518 , H01L21/28525 , H01L21/76802 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.
摘要翻译：本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。在本公开中，晶体管的源极和漏极由在源极和漏极处形成的通孔中形成的金属 - 半导体化合物接触区域和与源极和漏极相对应的通孔中的金属 - 半导体化合物引出。因为金属 - 半导体化合物具有相对低的电阻率，所以可以使过孔中金属 - 半导体化合物的电阻最小化。此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与金属 - 半导体化合物源极/漏极接触区域之间的接触电阻可以被最小化。此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏。因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

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