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1. 发明授权

US09215125B2 Techniques for connecting an external network coprocessor to a network processor packet parser 有权
标题翻译：将外部网络协处理器连接到网络处理器数据包解析器的技术
公开(公告)号：US09215125B2
公开(公告)日：2015-12-15
申请号：US13884664
申请日：2011-12-19
申请人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Damon Philippe , Natarajan Vaidhyanathan , Colin B. Verrilli , Fabrice Jean Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Damon Philippe , Natarajan Vaidhyanathan , Colin B. Verrilli , Fabrice Jean Verplanken
IPC分类号： H04L29/06 , G06F9/38 , G06F15/163 , G06F9/54
CPC分类号： H04L29/0653 , G06F9/3877 , G06F9/544 , G06F13/385 , G06F15/163 , H04L69/22
摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=
摘要翻译：网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =

2. 发明申请

US20130308653A1 Techniques for Connecting an External Network Coprocessor to a Network Processor Packet Parser 有权
标题翻译：将外部网络协处理器连接到网络处理器数据包解析器的技术
公开(公告)号：US20130308653A1
公开(公告)日：2013-11-21
申请号：US13884664
申请日：2011-12-19
申请人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Damon Philippe , Natarajan Vaidhyanathan , Colin B. Verrilli , Fabrice Jean Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Damon Philippe , Natarajan Vaidhyanathan , Colin B. Verrilli , Fabrice Jean Verplanken
IPC分类号： H04L29/06
CPC分类号： H04L29/0653 , G06F9/3877 , G06F9/544 , G06F13/385 , G06F15/163 , H04L69/22
摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=
摘要翻译：网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =

3. 发明申请

US20130266021A1 BUFFER MANAGEMENT SCHEME FOR A NETWORK PROCESSOR 审中-公开
标题翻译：网络处理器的缓冲区管理方案
公开(公告)号：US20130266021A1
公开(公告)日：2013-10-10
申请号：US13990587
申请日：2011-12-19
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Damon Philippe , Michel L. Poret , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Damon Philippe , Michel L. Poret , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/70
CPC分类号： H04L49/90 , G06F5/10 , G06F13/128
摘要： The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers is provided by software, in quantity large enough to support expected traffic. A Send Queue Replenisher (SQR) and Receive Queue Replenisher (RQR) hide RQ and SQ management to software. RQR and SQR fully monitor pointers queues and perform recirculation of pointers from transmit side to receive side.
摘要翻译：本发明提供了一种在接收端和发送端添加特定硬件的方法，其将隐藏与软件大部分与缓冲器和指针管理相关的功能的软件。在初始化时，一组指针和缓冲区由软件提供，数量足够大以支持预期流量。发送队列补货（SQR）和接收队列补货（RQR）将RQ和SQ管理隐藏到软件中。 RQR和SQR完全监视指针队列，并执行从发送端到接收端的指针的再循环。

4. 发明授权

US08942095B2 Identification of QoS classification based on packet attributes 有权
标题翻译：基于分组属性的QoS分类识别
公开(公告)号：US08942095B2
公开(公告)日：2015-01-27
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/54 , H04L12/851 , H04L29/06
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

5. 发明授权

US08675660B2 Selection of receive-queue based on packet attributes 失效
标题翻译：基于分组属性选择接收队列
公开(公告)号：US08675660B2
公开(公告)日：2014-03-18
申请号：US13466914
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28 , H04L12/54 , G06F15/173
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法。网络处理器接收数据包流中的第一数据包和适于存储接收数据包的一组接收队列。网络处理器通过读取第一数据分组中的流标识来处理第一数据分组; 确定第一数据分组的服务质量; 将流标识和服务质量映射到用于选择用于路由第一数据分组的第一接收队列的索引; 以及利用所述索引将所述第一数据分组路由到所述第一接收队列。

6. 发明授权

US07782888B2 Configurable ports for a host ethernet adapter 有权
标题翻译：主机以太网适配器的可配置端口
公开(公告)号：US07782888B2
公开(公告)日：2010-08-24
申请号：US11953820
申请日：2007-12-10
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

7. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

8. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

9. 发明授权

US07715428B2 Multicore communication processing 有权
标题翻译：多核通讯处理
公开(公告)号：US07715428B2
公开(公告)日：2010-05-11
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/66 , H04J3/16 , H04J3/22
CPC分类号： H04L47/50
摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了用于处理数据处理设备之间的通信的机制。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

10. 发明授权

US09088594B2 Providing to a parser and processors in a network processor access to an external coprocessor 有权
标题翻译：向网络处理器中的解析器和处理器提供对外部协处理器的访问
公开(公告)号：US09088594B2
公开(公告)日：2015-07-21
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/30 , H04L29/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

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