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1. 发明申请

US20090251071A1 Driving Multiple Parallel LEDs with Reduced Power Supply Ripple 有权
标题翻译：驱动具有降低电源纹波的多个并联LED
公开(公告)号：US20090251071A1
公开(公告)日：2009-10-08
申请号：US12099729
申请日：2008-04-08
申请人： Christian Gater , Roel Van Ettinger
发明人： Christian Gater , Roel Van Ettinger
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , G09G3/342 , G09G2320/064 , H05B33/0827
摘要： An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.
摘要翻译：公开了驱动并联连接的LED的LED驱动器。在普通的PWM亮度控制信号的控制下，不是同时对所有并联连接的LED施加电流，而是通过使用交错的亮度控制信号将每个并行路径的电流施加交错。不同并行路径中的LED的导通将具有相同的占空比，但是将不同步。这通过减小瞬时电流吸收器的幅度来减少电源中的纹波。在一个实施例中，移位寄存器包含PWM占空比的二进制表示，并且时钟沿移位寄存器移位位。 LED的每个并行路径的PWM亮度控制信号从沿着移位寄存器的不同位置被抽头，使得PWM亮度控制信号相同而交错。

2. 发明授权

US07843148B2 Driving multiple parallel LEDs with reduced power supply ripple 有权
标题翻译：驱动多个并联LED，降低电源纹波
公开(公告)号：US07843148B2
公开(公告)日：2010-11-30
申请号：US12099729
申请日：2008-04-08
申请人： Christian Gater , Roel Van Ettinger
发明人： Christian Gater , Roel Van Ettinger
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , G09G3/342 , G09G2320/064 , H05B33/0827
摘要： An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.
摘要翻译：公开了驱动并联连接的LED的LED驱动器。在普通的PWM亮度控制信号的控制下，不是同时对所有并联连接的LED施加电流，而是通过使用交错的亮度控制信号将每个并行路径的电流施加交错。不同并行路径中的LED的导通将具有相同的占空比，但是将不同步。这通过减小瞬时电流吸收器的幅度来减少电源中的纹波。在一个实施例中，移位寄存器包含PWM占空比的二进制表示，并且时钟沿着移位寄存器移位位。 LED的每个并行路径的PWM亮度控制信号从沿着移位寄存器的不同位置被抽头，使得PWM亮度控制信号相同而交错。

3. 发明申请

US20090244966A1 Threshold Evaluation Of EPROM Cells 有权
标题翻译： EPROM单元的阈值评估
公开(公告)号：US20090244966A1
公开(公告)日：2009-10-01
申请号：US12056570
申请日：2008-03-27
申请人： Paul Wilson , Roel Van Ettinger
发明人： Paul Wilson , Roel Van Ettinger
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C29/40 , G11C16/04 , G11C29/1201 , G11C29/50004 , G11C2029/0401 , G11C2207/104
摘要： Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired logic circuit to generate a single positive test result signal, and the failure of one or more of the embedded EPROM cells causes the wired logic circuit to generate a single negative test signal. A reference cell is also evaluated using a bias testing circuit to determine that the reference voltage supplied during normal operation is at an acceptable voltage level.
摘要翻译：评估主机IC器件中的嵌入式EPROM涉及使用程序电路对嵌入式EPROM的所有浮动栅极单元进行编程/解码，然后同时将预定的测试偏置电压传输到所有编程/未编程的浮动栅极单元，以及然后使用逻辑（例如，有线NOR或NAND）电路来评估所有浮栅单元的输出端，由此所有嵌入式EPROM单元的成功操作使得布线逻辑电路产生单个正测试结果信号，并且一个或多个嵌入式EPROM单元的故障使得布线逻辑电路产生单个负测试信号。还使用偏置测试电路来评估参考电池，以确定在正常操作期间提供的参考电压处于可接受的电压电平。

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