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1. 发明授权

US06191000B1 Shallow trench isolation method used in a semiconductor wafer 有权
标题翻译：在半导体晶片中使用的浅沟槽隔离方法
公开(公告)号：US06191000B1
公开(公告)日：2001-02-20
申请号：US09378700
申请日：1999-08-23
申请人： Chin-Yi Huang , Chin-Jen Huang , Chen-Chin Liu , Yun Chang
发明人： Chin-Yi Huang , Chin-Jen Huang , Chen-Chin Liu , Yun Chang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The invention relates to a shallow trench isolation method used in a semiconductor wafer that comprises a plurality of predetermined active regions, a plurality of shallow trenches used for electrically isolating the plurality of active regions, and a wafer alignment region wherein at least one recess having a predetermined pattern is formed on the surface of the wafer. In the method of the present invention, an insulation layer is first formed on the surface of the semiconductor wafer to fill the recesses in the wafer alignment region and the plurality of shallow trenches. An etching process is then implemented to reduce the thickness of the insulation layer on the surface of the working region, the working region having a relatively high density of active regions. Also, the insulation layer is completely removed from the recesses within the wafer alignment region. Finally, a chemical mechanical process (CMP) is performed on the surface of the semiconductor wafer to remove the insulation layer and to keep the surface of the insulation layer in the shallow trenches even with the semiconductor wafer.
摘要翻译：本发明涉及一种在半导体晶片中使用的浅沟槽隔离方法，其包括多个预定有源区，用于电隔离多个有源区的多个浅沟槽和晶片对准区域，其中至少一个具有在晶片的表面上形成预定图案。在本发明的方法中，首先在半导体晶片的表面上形成绝缘层，以填充晶片对准区域和多个浅沟槽中的凹槽。然后执行蚀刻工艺以减小工作区域表面上的绝缘层的厚度，工作区域具有较高密度的活性区域。此外，绝缘层完全从晶片对准区域内的凹部移除。最后，在半导体晶片的表面上进行化学机械工艺（CMP）以去除绝缘层，并且即使使用半导体晶片也能将绝缘层的表面保持在浅沟槽中。

2. 发明授权

US06576514B2 Method of forming a three-dimensional polysilicon layer on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成三维多晶硅层的方法
公开(公告)号：US06576514B2
公开(公告)日：2003-06-10
申请号：US09683213
申请日：2001-12-03
申请人： Chen-Chin Liu , Chin-Yi Huang , Weng-Hsing Huang
发明人： Chen-Chin Liu , Chin-Yi Huang , Weng-Hsing Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76819 , H01L27/115 , H01L29/66545
摘要： A semiconductor wafer includes a substrate, a polysilicon layer, and a sacrificial layer on the polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. A passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the sacrificial layer. The passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer, followed by removing the passivation layer and removing the sacrificial layer. A recess is thus formed with the polysilicon layer as the bottom of the recess and the remaining dielectric layer as the walls. Finally, another polysilicon layer is formed on the semiconductor wafer to form a floating gate.
摘要翻译：半导体晶片包括多晶硅层上的衬底，多晶硅层和牺牲层。形成介电层以覆盖基板和牺牲层。去除介电层的一部分以暴露牺牲层的侧壁的上部。在电介质层的表面上形成钝化层并与牺牲层的暴露的侧壁接触。位于牺牲层上的钝化层和电介质层通过CMP被去除到预定的高度。从牺牲层去除电介质层，然后去除钝化层并去除牺牲层。因此形成凹槽，其中多晶硅层作为凹槽的底部，剩余的电介质层作为壁。最后，在半导体晶片上形成另一个多晶硅层，形成浮栅。

3. 发明申请

US20110086482A1 APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE CELL WITH INCREASED OVERLAY BETWEEN THE CONTROL GATE AND FLOATING GATE 有权
标题翻译：用于制造在控制门和浮动闸门之间增加的浮动浇口池的装置和相关方法
公开(公告)号：US20110086482A1
公开(公告)日：2011-04-14
申请号：US12975737
申请日：2010-12-22
申请人： Chen-Chin Liu , Lan Ting Huang , Ling Kuey Yang , Po Hsuan Wu
发明人： Chen-Chin Liu , Lan Ting Huang , Ling Kuey Yang , Po Hsuan Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/11521
摘要： A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

4. 发明申请

US20060267079A1 Memory array including isolation between memory cell and dummy cell portions 有权
标题翻译：存储器阵列，包括存储器单元和虚拟单元部分之间的隔离
公开(公告)号：US20060267079A1
公开(公告)日：2006-11-30
申请号：US11137476
申请日：2005-05-26
申请人： Lan-Ting Huang , Chen-Chin Liu , Cheng Liu
发明人： Lan-Ting Huang , Chen-Chin Liu , Cheng Liu
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.
摘要翻译：半导体存储器件结构包括沿着与虚设单元部分相邻的存储单元部分的边缘形成的隔离区域，以将存储单元部分与在虚设单元部分中产生的泄漏电流隔离。

5. 发明授权

US06468864B1 Method of fabricating silicon nitride read only memory 有权
标题翻译：制造氮化硅只读存储器的方法
公开(公告)号：US06468864B1
公开(公告)日：2002-10-22
申请号：US09927645
申请日：2001-08-10
申请人： Jiann-Long Sung , Chen-Chin Liu , Chia-Hsing Chen
发明人： Jiann-Long Sung , Chen-Chin Liu , Chia-Hsing Chen
IPC分类号： H01L21331
CPC分类号： H01L29/66833 , H01L29/792
摘要： A method of fabricating silicon nitride read only memory. A trapping layer is formed on a substrate. Next, a patterned photoresist layer is formed, and the substrate region at the lower section of the trapping layer masked by the photoresist layer is defined as a channel region. The substrate region at the lower section of the trapping layer and no masked by the photoresist layer is defined as a source/drain region. Next, a pocket ion implantation is performed while using the photoresist layer as amask, and a first dopant is implanted into the source/drain region of the substrate. The photoresist layer is used as a mask and the source/drain ions are implanted. A second dopant is implanted into the source/drain region of the substrate. After that, the photoresist layer is removed. Next, the trapping layer is used as a mask, and a thermal process is performed so that the substrate surface of the source/drain region forms a buried source/drain oxide layer, while at the same time, the second dopant at the lower section of the buried source/drain oxide layer forms a buried source/drain. The first dopant forms the pocket doping region at the edge of the channel region of the buried source/drain periphery as a result of thermal diffusion. Finally, a conductive gate is formed on the substrate.
摘要翻译：一种制造氮化硅只读存储器的方法。在基板上形成捕获层。接下来，形成图案化的光致抗蚀剂层，并且由光致抗蚀剂层掩蔽的捕获层的下部的基板区域被定义为沟道区域。捕获层的下部的基板区域被光致抗蚀剂层掩蔽，被定义为源极/漏极区域。接下来，使用光致抗蚀剂层作为掩模进行袋式离子注入，并且将第一掺杂剂注入到衬底的源极/漏极区域中。光致抗蚀剂层用作掩模，并且注入源/漏离子。将第二掺杂剂注入到衬底的源极/漏极区域中。之后，去除光致抗蚀剂层。接下来，将捕获层用作掩模，并且进行热处理，使得源极/漏极区域的衬底表面形成掩埋源极/漏极氧化物层，同时在下部的第二掺杂剂的掩埋源极/漏极氧化物层形成埋入的源极/漏极。作为热扩散的结果，第一掺杂剂在掩埋源极/漏极周边的沟道区域的边缘处形成腔体掺杂区域。最后，在基板上形成导电栅极。

6. 发明授权

US08354335B2 Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate 有权
标题翻译：用于制造浮动栅极单元的装置和相关方法，其在控制栅极和浮动栅极之间具有增加的覆盖
公开(公告)号：US08354335B2
公开(公告)日：2013-01-15
申请号：US12975737
申请日：2010-12-22
申请人： Chen-Chin Liu , Lan Ting Huang , Ling Kuey Yang , Po Hsuan Wu
发明人： Chen-Chin Liu , Lan Ting Huang , Ling Kuey Yang , Po Hsuan Wu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/11521
摘要： A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用在浮置栅极之下的掩埋扩散氧化物，从而在浮置栅极和掩埋扩散氧化物之间产生增加的台阶高度。增加的台阶高度可以产生更高的GCR，而仍然允许使用虚拟接地阵列设计减小单元尺寸。

7. 发明授权

US06869843B2 Non-volatile memory cell with dielectric spacers along sidewalls of a component stack, and method for forming same 有权
公开(公告)号：US06869843B2
公开(公告)日：2005-03-22
申请号：US10609075
申请日：2003-06-27
申请人： Fu-Shiung Hsu , Chen-Chin Liu
发明人： Fu-Shiung Hsu , Chen-Chin Liu
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L21/8247
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/792 , Y10S438/954
摘要： A disclosed method for forming a non-volatile memory cell includes forming a component stack including an electron trapping layer on a substrate surface. A dielectric layer is formed over the component stack, and a portion is removed such that a remainder of the dielectric layer exists substantially along sidewalls of the component stack. An oxide layer is formed over a bit line in the substrate adjacent to the component stack, and an electrically conductive layer is formed over the component stack and the oxide layer. A described non-volatile memory cell includes a component stack on a substrate surface, the component stack including an electron trapping layer. Multiple dielectric spacers are positioned along sidewalls of the component stack. An oxide layer is positioned over a bit line in the substrate adjacent to the component stack, and an electrically conductive layer is positioned over the component stack and the oxide layer.

8. 发明申请

US20050026309A1 [METHOD OF INCREASING CELL RETENTION CAPACITY OF SILICON NITRIDE READ-ONLY-MEMORY CELL] 有权
标题翻译： [增加硅化钠只读存储单元的细胞保持能力的方法]
公开(公告)号：US20050026309A1
公开(公告)日：2005-02-03
申请号：US10709603
申请日：2004-05-17
申请人： Kuen-Chi Chuang , Chen-Chin Liu , Jiong-Zhong Chen
发明人： Kuen-Chi Chuang , Chen-Chin Liu , Jiong-Zhong Chen
IPC分类号： H01L21/28 , H01L21/66 , H01L21/336
CPC分类号： H01L22/20 , H01L21/28282
摘要： A method of increasing the cell retention capacity of a silicon nitride read-only-memory on a wafer. The method includes carrying out a baking process after performing the last plasma treatment of the wafer but before a wafer sort test.
摘要翻译：提高晶圆上氮化硅只读存储器的电池保持容量的方法。该方法包括在进行晶片的最后等离子体处理之后但在晶片分类测试之前执行烘焙处理。

9. 发明授权

US06501123B2 High gate coupling non-volatile memory structure 有权
标题翻译：高栅极耦合非易失性存储器结构
公开(公告)号：US06501123B2
公开(公告)日：2002-12-31
申请号：US09878897
申请日：2001-06-11
申请人： Chen-Chin Liu
发明人： Chen-Chin Liu
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure having a higher gate-coupling ratio. The structure includes a substrate, shallow trench isolation layers, buried source/drain terminals, tunnel oxide layers, a floating gate with a three-dimensional structure, dielectric layers and a control gate. A portion of the floating gate is located inside an opening in the dielectric layer so that a three-dimensional structure formed. Since the subsequently formed control gate has a larger effective surface area, a higher gate-coupling ratio is obtained.
摘要翻译：具有较高栅极耦合比的非易失性存储器结构。该结构包括衬底，浅沟槽隔离层，埋地源极/漏极端子，隧道氧化物层，具有三维结构的浮动栅极，介电层和控制栅极。浮动栅极的一部分位于电介质层的开口内部，从而形成三维结构。由于随后形成的控制栅极具有较大的有效表面积，所以获得更高的栅极耦合比。

10. 发明授权

US08017480B2 Apparatus and associated method for making a floating gate cell in a virtual ground array 有权
标题翻译：用于在虚拟接地阵列中制造浮动栅极单元的装置和相关方法
公开(公告)号：US08017480B2
公开(公告)日：2011-09-13
申请号：US11423842
申请日：2006-06-13
申请人： Chen-Chin Liu , Chun-Pei Wu , Ta-Kang Chu , Yao-Fu Chan
发明人： Chen-Chin Liu , Chun-Pei Wu , Ta-Kang Chu , Yao-Fu Chan
IPC分类号： H01L21/8234
CPC分类号： H01L29/4234 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L29/42324
摘要： A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.
摘要翻译：一种用于制造浮动栅极存储器件的方法，包括使用较薄的掩埋扩散区，其中埋入扩散氧化物层的埋入扩大到掩埋扩散层内并在浮动栅极下方的隧道氧化物下面。此外，浮置栅极多晶硅层具有比掩埋扩散高度更大的高度。栅极多晶硅层对掩埋扩散层的阶梯高度增加以及掩埋扩散氧化物的侵蚀增加，可以产生较高的GCR，同时仍然允许使用虚拟接地阵列设计减小电池尺寸。

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