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1. 发明授权

US07254059B2 Multilevel phase-change memory element and operating method 失效
标题翻译：多级相变存储元件及操作方法
公开(公告)号：US07254059B2
公开(公告)日：2007-08-07
申请号：US11182783
申请日：2005-07-18
申请人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
发明人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
IPC分类号： G11C11/34
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2013/008 , G11C2013/009 , G11C2213/78 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/165
摘要： A multilevel phase change memory element and operating method and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory element such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory element has more bits and higher capacity than that of a memory element with a single phase-change layer.
摘要翻译：多级相变存储器元件和操作方法和电极，其被配置为并行结构以形成存储器单元。采用电压驱动模式来控制和驱动存储元件，使得可以通过施加不同的电压电平来实现多电平存储器状态。所提供的多电平相变存储器元件具有比具有单个相变层的存储器元件更多的位和更高的容量。

2. 发明申请

US20070249083A1 Multilevel phase-change memory element and operating method 审中-公开
标题翻译：多级相变存储元件及操作方法
公开(公告)号：US20070249083A1
公开(公告)日：2007-10-25
申请号：US11819063
申请日：2007-06-25
申请人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
发明人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
IPC分类号： H01L31/0376
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2013/008 , G11C2013/009 , G11C2213/78 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/165
摘要： A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory has more bits and higher capacity than that of the memory with a single phase-change layer.
摘要翻译：多级相变存储器，其操作方法及其制造方法。相变存储器包括两个相变层和电极，其被配置成并联结构以形成存储单元。使用电压驱动模式来控制和驱动存储器，使得可以通过施加不同的电压电平来实现多电平存储器状态。所提供的多电平相变存储器具有比具有单个相变层的存储器更多的位和更高的容量。

3. 发明申请

US20060077706A1 Multilevel phase-change memory, operating method and manufacture method thereof 失效
标题翻译：多级相变存储器，其操作方法及其制造方法
公开(公告)号：US20060077706A1
公开(公告)日：2006-04-13
申请号：US11182783
申请日：2005-07-18
申请人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
发明人： Chien-Ming Li , Wen-Han Wang , Kuei-Hung Shen
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2013/008 , G11C2013/009 , G11C2213/78 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/165
摘要： A multilevel phase-change memory, operating method and manufacturing method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory has more bits and higher capacity than that of the memory with a single phase-change layer.
摘要翻译：多级相变存储器，其操作方法及其制造方法。相变存储器包括两个相变层和电极，其被配置成并联结构以形成存储单元。使用电压驱动模式来控制和驱动存储器，使得可以通过施加不同的电压电平来实现多电平存储器状态。所提供的多电平相变存储器具有比具有单个相变层的存储器更多的位和更高的容量。

4. 发明申请

US20060077741A1 Multilevel phase-change memory, manufacturing and status transferring method thereof 审中-公开
标题翻译：多级相变存储器，其制造和状态转移方法
公开(公告)号：US20060077741A1
公开(公告)日：2006-04-13
申请号：US11182866
申请日：2005-07-18
申请人： Wen-Han Wang , Chien-Ming Li , Kuei-Hung Shen
发明人： Wen-Han Wang , Chien-Ming Li , Kuei-Hung Shen
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A multilevel phase-change memory, manufacturing method and status transferring method thereof. The phase-change memory includes two phase-change layers and electrodes, which are configured in a series structure to form a memory cell. A current-drive mode is employed to control and drive the memory such that multilevel memory states may be achieved by imposing different current levels. The provided multilevel phase-change memory has more bits and higher capacity than that of the memory with a single phase-change layer. Furthermore, the series structure may reduce the cell area and the device volume.
摘要翻译：多级相变存储器，其制造方法和状态转移方法。相变存储器包括两个相变层和电极，其被构造成串联结构以形成存储单元。采用电流驱动模式来控制和驱动存储器，使得可以通过施加不同的电流电平来实现多电平存储器状态。所提供的多电平相变存储器具有比具有单个相变层的存储器更多的位和更高的容量。此外，串联结构可以减小单元面积和器件体积。

5. 发明申请

US20070148855A1 Phase change memory device and fabricating method therefor 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070148855A1
公开(公告)日：2007-06-28
申请号：US11479497
申请日：2006-06-30
申请人： Wei-Su Chen , Yi-Chan Chen , Wen-Han Wang , Hong-Hui Hsu , Chien-Min Lee , Yen Chuo , Te-Sheng Chao , Min-Hung Lee
发明人： Wei-Su Chen , Yi-Chan Chen , Wen-Han Wang , Hong-Hui Hsu , Chien-Min Lee , Yen Chuo , Te-Sheng Chao , Min-Hung Lee
IPC分类号： H01L21/8244 , H01L21/8238 , H01L21/00 , H01L21/20
CPC分类号： H01L45/06 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.
摘要翻译：提供了一种相变存储器件及其制造方法。盘状相变层被埋在绝缘材料内。通过光刻形成中心通孔和环形通孔。中心通孔位于相变层的中心，通过相变层，环形通孔以中心通孔为中心。中心通孔内的加热电极进行相变层的焦耳加热，通过控制相变层的厚度来降低相变层与加热电极之间的接触面积。此外，环通孔内的第二电极耗散了传递到相变层之间的接触界面的热量，以避免将热量传递到相变层周围的蚀刻边界。

6. 发明申请

US20070120105A1 Lateral phase change memory with spacer electrodes and method of manufacturing the same 失效
标题翻译：具有间隔电极的侧向相变存储器及其制造方法
公开(公告)号：US20070120105A1
公开(公告)日：2007-05-31
申请号：US11435276
申请日：2006-05-17
申请人： Te-Sheng Chao , Wen-Han Wang , Min-Hung Lee , Hong-Hui Hsu , Chien-Min Lee , Yen Chuo , Yi-Chan Chen , Wei-Su Chen
发明人： Te-Sheng Chao , Wen-Han Wang , Min-Hung Lee , Hong-Hui Hsu , Chien-Min Lee , Yen Chuo , Yi-Chan Chen , Wei-Su Chen
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1226 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the phase change material contacts the spacer electrodes and the volume of the phase change material can be reduced; thereby the programming current and power consumption of the phase change memory are reduced.
摘要翻译：提供了具有间隔电极的横向相变存储器及其制造方法。存储器通过以较低的电阻率连接导电电极和具有较高电阻率的间隔电极而形成，并且填充间隔电极之间的相变材料。因此，可以减少相变材料与间隔电极接触的面积和相变材料的体积; 从而降低了相变存储器的编程电流和功耗。

7. 发明申请

US20070007613A1 Phase change memory with adjustable resistance ratio and fabricating method thereof 审中-公开
标题翻译：具有可调电阻比的相变存储器及其制造方法
公开(公告)号：US20070007613A1
公开(公告)日：2007-01-11
申请号：US11240449
申请日：2005-10-03
申请人： Wen-Han Wang , Jiuh-Ming Liang , Jyi-Tyan Yeh , Shan-Haw Chiou
发明人： Wen-Han Wang , Jiuh-Ming Liang , Jyi-Tyan Yeh , Shan-Haw Chiou
IPC分类号： H01L31/058 , H01L29/06 , H01L29/02 , H01L47/00 , G11C11/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144 , H01L45/1675
摘要： A phase change memory with adjustable resistance ratio is disclosed, which includes a phase change layer and an interfacial layer formed to be in contact with each other, and at least two electrodes in contact with the phase change layer and the interfacial layer respectively. The contact sections between the two electrodes and the phase change layer and the interfacial layer define a contact area respectively, wherein, the area defined by the contact section between the electrode and the phase change layer is larger than the area defined by the contact section between the electrode and the interfacial layer.
摘要翻译：公开了具有可调电阻比的相变存储器，其包括形成为彼此接触的相变层和界面层，以及分别与相变层和界面层接触的至少两个电极。两个电极与相变层和界面层之间的接触部分分别限定接触面积，其中由电极和相变层之间的接触部分限定的面积大于由电极和相变层之间的接触部分限定的面积电极和界面层。

8. 发明授权

US09184586B2 SiGe based gate driven PMOS trigger circuit 有权
标题翻译：基于SiGe的栅极驱动PMOS触发电路
公开(公告)号：US09184586B2
公开(公告)日：2015-11-10
申请号：US13533059
申请日：2012-06-26
申请人： Wen-Han Wang , Kuo-Ji Chen
发明人： Wen-Han Wang , Kuo-Ji Chen
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , Y10T29/49117
摘要： Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.
摘要翻译：本公开的一些实施例涉及向ESD敏感电路提供ESD保护的低功率，区域有效的ESD保护装置。 ESD保护器件具有带电阻器的触发电路。电阻器具有连接到第一外部引脚的第一端子和直接连接到基于SiGe的PMOS分流晶体管的栅极的第二端子。当存在ESD事件时，触发电路产生驱动PMOS器件的栅极的触发信号，以将电源从ESD易受损害的电路分流。基于SiGe的PMOS分流晶体管具有比常规NMOS分流晶体管更低的栅极泄漏，从而在小栅极长度处提供具有低漏电流的ESD电路。

9. 发明授权

US08648425B2 Resistors formed based on metal-oxide-semiconductor structures 有权
标题翻译：基于金属氧化物半导体结构形成的电阻器
公开(公告)号：US08648425B2
公开(公告)日：2014-02-11
申请号：US13170751
申请日：2011-06-28
申请人： Wen-Han Wang , Chen-Chih Wu , Sheng-Fang Cheng , Kuo-Ji Chen
发明人： Wen-Han Wang , Chen-Chih Wu , Sheng-Fang Cheng , Kuo-Ji Chen
IPC分类号： H01L27/06
CPC分类号： H01L28/20 , H01L27/0629
摘要： A device includes a metal-oxide-semiconductor (MOS) device, which includes a gate electrode and a source/drain region adjacent the gate electrode. A first and a second contact plug are formed directly over and electrically connected to two portions of a same MOS component, wherein the same MOS component is one of the gate electrode and the source/drain region. The same MOS component is configured to be used as a resistor that is connected between the first and the second contact plugs.
摘要翻译：一种器件包括金属氧化物半导体（MOS）器件，其包括栅电极和与栅电极相邻的源/漏区。第一和第二接触插塞形成在相同的MOS部件的两部分上方并电连接，其中相同的MOS部件是栅极电极和源极/漏极区域之一。相同的MOS部件被配置为用作连接在第一和第二接触插塞之间的电阻器。

10. 发明申请

US20130342941A1 SIGE BASED GATE DRIVEN PMOS TRIGGER CIRCUIT 有权
标题翻译：基于信号的栅极驱动PMOS触发电路
公开(公告)号：US20130342941A1
公开(公告)日：2013-12-26
申请号：US13533059
申请日：2012-06-26
申请人： Wen-Han Wang , Kuo-Ji Chen
发明人： Wen-Han Wang , Kuo-Ji Chen
IPC分类号： H02H9/04 , H01R43/00
CPC分类号： H02H9/046 , Y10T29/49117
摘要： Some embodiments of the present disclosure relate to a low-power, area efficient ESD protection device that provides ESD protection to an ESD susceptible circuit. The ESD protection device has a trigger circuit with a resistor. The resistor has a first terminal connected to the first external pin and a second terminal connected directly to a gate of a SiGe based PMOS shunt transistor. The trigger circuit generates a trigger signal that drives the gate of the PMOS device to shunt power away from the ESD susceptible circuit when an ESD event is present. The SiGe based PMOS shunt transistor has a lower gate leakage than a conventional NMOS shunt transistors, thereby providing for an ESD circuit with a low leakage current at small gate lengths.
摘要翻译：本公开的一些实施例涉及向ESD敏感电路提供ESD保护的低功率，区域有效的ESD保护装置。 ESD保护器件具有带电阻器的触发电路。电阻器具有连接到第一外部引脚的第一端子和直接连接到基于SiGe的PMOS分流晶体管的栅极的第二端子。当存在ESD事件时，触发电路产生驱动PMOS器件的栅极的触发信号，以将电源从ESD易受损害的电路分流。基于SiGe的PMOS分流晶体管具有比常规NMOS分流晶体管更低的栅极泄漏，从而在小栅极长度处提供具有低漏电流的ESD电路。

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