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1. 发明申请

US20100156888A1 Adaptive mapping for heterogeneous processing systems 审中-公开
标题翻译：异构处理系统的自适应映射
公开(公告)号：US20100156888A1
公开(公告)日：2010-06-24
申请号：US12317450
申请日：2008-12-23
申请人： Chi-Keung Luk , Paul Geoffrey Lowney
发明人： Chi-Keung Luk , Paul Geoffrey Lowney
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： Embodiments of a system, program product and method are presented to perform automatic partitioning of work between host processor (such as, e.g., a CPU) and at least one additional heterogeneous processing element (such as, e.g., a GPU) through run-time adaptive mapping. The adaptive mapping may be performed by a dynamic compiler, based on projected execution times predicted by curve fitting based on actual execution times generated during a profile run of the program. Other embodiments are described and claimed.
摘要翻译：呈现系统，程序产品和方法的实施例，以通过运行时间来执行主处理器（例如，CPU）和至少一个附加异构处理元件（例如，GPU）之间的工作的自动分区自适应映射。基于基于在程序的轮廓运行期间产生的实际执行时间的曲线拟合所预测的执行时间，动态编译器可以执行自适应映射。描述和要求保护其他实施例。

2. 发明申请

US20050050534A1 Methods and apparatus to pre-execute instructions on a single thread 审中-公开
标题翻译：在单个线程上预执行指令的方法和装置
公开(公告)号：US20050050534A1
公开(公告)日：2005-03-03
申请号：US10653602
申请日：2003-09-02
申请人： Chi-Keung Luk , Paul Lowney
发明人： Chi-Keung Luk , Paul Lowney
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Methods and apparatus to pre-execute instructions on a single thread are disclosed. In an example method, at least one instruction associated with a latency condition is identified. A slice of instructions is identified. The slice of instructions is configured to generate a data address associated with the at least one instruction. At least one instruction slot in the single thread is identified. Code configured to execute the slice of instructions is generated within the at least one instruction slot.
摘要翻译：公开了在单个线程上预执行指令的方法和装置。在示例性方法中，识别与等待时间条件相关联的至少一个指令。识别一段指令。所述指令片被配置为生成与所述至少一个指令相关联的数据地址。识别单线程中至少有一个指令槽。被配置为执行指令片段的代码在至少一个指令槽内产生。

3. 发明授权

US07343602B2 Software controlled pre-execution in a multithreaded processor 有权
标题翻译：软件控制在多线程处理器中的预执行
公开(公告)号：US07343602B2
公开(公告)日：2008-03-11
申请号：US10029699
申请日：2001-12-18
申请人： Chi-Keung Luk , Joel S. Emer
发明人： Chi-Keung Luk , Joel S. Emer
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00
CPC分类号： G06F9/4843 , G06F8/4442 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/141 , G06F11/1497
摘要： A processor capable of running multiple threads runs a program in one thread (called the “main” thread) and at least a portion of the same program in another thread (called the “pre-execution” thread). The program in the main thread includes instructions that cause the processor to start and stop pre-execution threads and direct the processor as to which part of the program is to be run through the pre-execution threads. Preferably, such instructions cause the pre-execution thread to run ahead of the main thread in program order. In that way, any cache miss conditions that are encountered by the pre-execution thread are resolved before the main thread requires that same data. Therefore, the main thread should encounter few or no cache miss conditions.
摘要翻译：能够运行多个线程的处理器在一个线程（称为“主”线程）中运行程序，并在另一个线程（称为“预执行”线程）中运行相同程序的至少一部分。主线程中的程序包括使处理器启动和停止预执行线程并将处理器指示为通过预执行线程运行程序的哪些部分的指令。优选地，这样的指令使得预执行线程以程序顺序在主线程之前运行。以这种方式，预执行线程遇到的任何高速缓存未命中情况都在主线程需要相同数据之前解决。因此，主线程应该遇到很少或没有缓存未命中的条件。

4. 发明申请

US20070234307A1 Methods and apparatus to inline conditional software instrumentation 审中-公开
标题翻译：在线条件软件仪器的方法和装置
公开(公告)号：US20070234307A1
公开(公告)日：2007-10-04
申请号：US11369051
申请日：2006-03-06
申请人： Chi-Keung Luk , Robert Cohn
发明人： Chi-Keung Luk , Robert Cohn
IPC分类号： G06F9/44
CPC分类号： G06F11/3644
摘要： Methods and apparatus to inline conditional software instrumentation are disclosed. An example method comprises splitting a software instrumentation conditional analysis procedure for an application segment into an unconditional portion and a conditional portion, and inlining the unconditional portion.
摘要翻译：披露了在线条件软件仪器的方法和装置。一种示例性方法包括将用于应用程序段的软件工具条件分析过程分解成无条件部分和条件部分，以及内联无条件部分。

5. 发明授权

US07181723B2 Methods and apparatus for stride profiling a software application 有权
标题翻译：软件应用程序分析的方法和装置
公开(公告)号：US07181723B2
公开(公告)日：2007-02-20
申请号：US10446004
申请日：2003-05-27
申请人： Chi-Keung Luk , Geoff Lowney
发明人： Chi-Keung Luk , Geoff Lowney
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Methods and an apparatus for stride profiling a software application are disclosed. An example system uses a hardware performance counter to report instruction addresses and data addresses associated with memory access instructions triggered by some event, such as a data cache miss. When the same instruction address is associated with more than one data address, the difference between the two data addresses is recorded. When two or more of these data address differences are recorded for the same instruction, the system determines a stride associated with the instruction to be the greatest common divisor of the two or more differences. This stride may be used by a compiler to optimize data cache prefetching. In addition, any overhead associated with monitoring addresses of data cache misses may be reduced by cycling between an inspection phase and a skipping phase. More data cache misses are monitored during the inspection phase than during the skipping phase.
摘要翻译：公开了用于跨越软件应用程序的方法和装置。示例系统使用硬件性能计数器来报告与诸如数据高速缓存未命中的某些事件触发的存储器访问指令相关联的指令地址和数据地址。当相同的指令地址与多个数据地址相关联时，记录两个数据地址之间的差异。当对于相同的指令记录这些数据地址差异中的两个或更多个时，系统确定与指令相关联的步长是两个或更多个差异的最大公约数。编译器可以使用这一步来优化数据缓存预取。此外，通过在检查阶段和跳过阶段之间的循环可以减少与监视数据高速缓存未命中地址相关联的任何开销。在检查阶段监视更多的数据高速缓存未命中，而不是在跳过阶段。

6. 发明申请

US20070006167A1 Optimizing binary-level instrumentation via instruction scheduling 审中-公开
标题翻译：通过指令调度优化二进制级别的仪器
公开(公告)号：US20070006167A1
公开(公告)日：2007-01-04
申请号：US11140841
申请日：2005-05-31
申请人： Chi-Keung Luk , Ady Tal , Robert Cohn , Jonathan Beimel
发明人： Chi-Keung Luk , Ady Tal , Robert Cohn , Jonathan Beimel
IPC分类号： G06F9/44
CPC分类号： G06F9/45525 , G06F8/443
摘要： In one embodiment, the present invention includes a method for receiving a command to insert instrumentation code into a code segment, analyzing the code segment to determine an optimal location for the instrumentation code within the code segment, and inserting the instrumentation code at the optimal location to generate an instrumented code segment. The instrumented code segment may then be executed and may provide for improved performance over unoptimized instrumented code. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种方法，用于接收将检验代码插入代码段的命令，分析代码段以确定代码段内的检测代码的最佳位置，以及将检测代码插入到最佳位置生成一个乐器化代码段。然后可以执行检测的代码段，并且可以提供未优化的仪表化代码的改进的性能。描述和要求保护其他实施例。

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