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1. 发明申请

US20180041450A1 PROTOCOL INDEPENDENT PROGRAMMABLE SWITCH (PIPS) FOR SOFTWARE DEFINED DATA CENTER NETWORKS 审中-公开
公开(公告)号：US20180041450A1
公开(公告)日：2018-02-08
申请号：US15786900
申请日：2017-10-18
申请人： Cavium, Inc.
发明人： Guy Townsend Hutchison , Sachin Ramesh Gandhi , Tsahi Daniel , Gerald Schmidt , Albert Fishman , Martin Leslie White , Zubin Shah
IPC分类号： H04L12/933 , H04L29/08 , H04L12/935 , H04L12/715 , G06F3/06 , G06F17/30 , G06F17/27 , H04L29/06 , H04L12/741
摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

2. 发明授权

US09990324B2 Two modes of a configuration interface of a network ASIC 有权
公开(公告)号：US09990324B2
公开(公告)日：2018-06-05
申请号：US14521354
申请日：2014-10-22
申请人： CAVIUM, INC.
发明人： Guy Townsend Hutchison , Harish Krishnamoorthy , Gerald Schmidt , Vishal Anand
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4068 , G06F13/4221
摘要： Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

3. 发明授权

US10785169B2 Protocol independent programmable switch (PIPS) for software defined data center networks 有权
公开(公告)号：US10785169B2
公开(公告)日：2020-09-22
申请号：US15786900
申请日：2017-10-18
申请人： Cavium, Inc.
发明人： Guy Townsend Hutchison , Sachin Ramesh Gandhi , Tsahi Daniel , Gerald Schmidt , Albert Fishman , Martin Leslie White , Zubin Shah
IPC分类号： H04L12/933 , H04L12/715 , H04L12/741 , H04L29/06 , H04L29/08 , G06F16/00 , G06F40/205 , G06F3/06 , H04L12/935
摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

4. 发明申请

US20180246836A1 TWO MODES OF A CONFIGURATION INTERFACE OF A NETWORK ASIC 审中-公开
公开(公告)号：US20180246836A1
公开(公告)日：2018-08-30
申请号：US15969681
申请日：2018-05-02
申请人： Cavium Inc.
发明人： Guy Townsend Hutchison , Harish Krishnamoorthy , Gerald Schmidt , Vishal Anand
IPC分类号： G06F13/40 , G06F13/42
摘要： Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

5. 发明授权

US09542342B2 Smart holding registers to enable multiple register accesses 有权
标题翻译：智能保持寄存器以启用多个寄存器访问
公开(公告)号：US09542342B2
公开(公告)日：2017-01-10
申请号：US14521359
申请日：2014-10-22
申请人： CAVIUM, INC.
发明人： Vishal Anand , Harish Krishnamoorthy , Guy Townsend Hutchison
IPC分类号： G06F12/00 , G06F13/16 , G06F9/52 , G06F9/30
CPC分类号： G06F13/1663 , G06F9/30098 , G06F9/52
摘要： A multiple access mechanism allows sources to simultaneously access different target registers at the same time without using a semaphore. The multiple access mechanism is implemented using N holding registers and source identifiers. The N holding registers are located in each slave engine. Each of the N holding registers is associated with a source and is configured to receive partial updates from the source before pushing the full update to a target register. After the source is finished updating the holding register and the holding register is ready to commit to the target register, a source identifier is added to a register bus. The source identifier identifies the holding register as the originator of the transaction on the register bus. The N holding registers are able to simultaneously handle N register transactions. The max value of N is 2n, where n is the number of bits in the source identifier.
摘要翻译：多访问机制允许源同时访问不同目标寄存器，而不使用信号量。使用N个保持寄存器和源标识符来实现多址机制。 N个保持寄存器位于每个从动引擎中。 N个保持寄存器中的每一个与源相关联，并且被配置为在将完整更新推送到目标寄存器之前从源接收部分更新。在源更新保持寄存器并且保持寄存器准备好提交到目标寄存器之后，源标识符被添加到寄存器总线。源标识符将保持寄存器标识为寄存器总线上事务的发起者。 N个保持寄存器能够同时处理N个寄存器事务。 N的最大值为2n，其中n是源标识符中的位数。

6. 发明授权

US10579573B2 Method of implementing a network ASIC in a network device 有权
公开(公告)号：US10579573B2
公开(公告)日：2020-03-03
申请号：US15969681
申请日：2018-05-02
申请人： Cavium Inc.
发明人： Guy Townsend Hutchison , Harish Krishnamoorthy , Gerald Schmidt , Vishal Anand
IPC分类号： G06F13/40 , G06F13/42
摘要： Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at least one decoder. A decoder includes logic that determines which of its leaves to send an external access transaction to. In contrast, if a module is not the target node, then the module passes an external access transaction to the next node coupled thereto; otherwise, if the module is the target node, the transmission of the external access transaction stops at the module.

7. 发明授权

US10078605B2 Multiple-interrupt propagation scheme in a network ASIC 有权
公开(公告)号：US10078605B2
公开(公告)日：2018-09-18
申请号：US14521367
申请日：2014-10-22
申请人： CAVIUM, INC.
发明人： Vishal Anand , Harish Krishnamoorthy , Guy Townsend Hutchison , Gerald Schmidt
IPC分类号： G06F13/26
CPC分类号： G06F13/26
摘要： Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

8. 发明申请

US20160197852A1 PROTOCOL INDEPENDENT PROGRAMMABLE SWITCH (PIPS) SOFTWARE DEFINED DATA CENTER NETWORKS 有权
标题翻译：协议独立可编程开关（PIPS）软件定义数据中心网络
公开(公告)号：US20160197852A1
公开(公告)日：2016-07-07
申请号：US15067139
申请日：2016-03-10
申请人： Cavium, Inc.
发明人： Guy Townsend Hutchison , Sachin Gandhi , Tsahi Daniel , Gerald Schmidt , Albert Fishman , Martin Leslie White , Zubin Shah
IPC分类号： H04L12/933 , G06F17/27 , H04L12/935 , H04L12/741 , H04L29/06 , H04L29/08 , G06F3/06 , H04L12/715
CPC分类号： H04L49/109 , G06F3/0604 , G06F3/064 , G06F3/0656 , G06F3/0673 , G06F17/2705 , G06F17/30 , H04L45/64 , H04L45/74 , H04L45/745 , H04L49/1546 , H04L49/3018 , H04L67/327 , H04L69/22
摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.
摘要翻译：软件定义网络（SDN）系统，设备和方法包括一个或多个输入端口，可编程解析器，多个可编程查找和决策引擎（LDE），可编程查找存储器，可编程计数器，可编程重写块和一个或更多的输出端口。解析器，LDE，查找存储器，计数器和重写块的可编程性使得用户能够根据需要将系统内的每个微芯片定制到特定分组环境，数据分析需求，分组处理功能和其他功能。此外，相同的微芯片能够被动态地重新编程用于其他目的和/或优化。

9. 发明授权

US09825884B2 Protocol independent programmable switch (PIPS) software defined data center networks 有权
公开(公告)号：US09825884B2
公开(公告)日：2017-11-21
申请号：US15067139
申请日：2016-03-10
申请人： Cavium, Inc.
发明人： Guy Townsend Hutchison , Sachin Gandhi , Tsahi Daniel , Gerald Schmidt , Albert Fishman , Martin Leslie White , Zubin Shah
IPC分类号： G06F17/30 , H04L12/933 , G06F3/06 , G06F17/27 , H04L12/715 , H04L12/741 , H04L29/06 , H04L29/08 , H04L12/935
CPC分类号： H04L49/109 , G06F3/0604 , G06F3/064 , G06F3/0656 , G06F3/0673 , G06F17/2705 , G06F17/30 , H04L45/64 , H04L45/74 , H04L45/745 , H04L49/1546 , H04L49/3018 , H04L67/327 , H04L69/22
摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

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