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1. 发明授权

US06797613B2 Process for depositing WSix layers on a high topography with a defined stoichiometry 有权
标题翻译：使用定义的化学计量在高地形上沉积WSix层的方法
公开(公告)号：US06797613B2
公开(公告)日：2004-09-28
申请号：US10196698
申请日：2002-07-16
申请人： Bernhard Sell , Annette Sänger , Georg Schulze-Icking
发明人： Bernhard Sell , Annette Sänger , Georg Schulze-Icking
IPC分类号： H01L21443
CPC分类号： H01L21/28556 , H01L21/28518
摘要： Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.
摘要翻译：在衬底上形成硅化钨层，并且半导体部件具有填充硅化钨的深沟槽电容器。硅化钨层在低于400℃的温度和低于10托的压力下沉积在基底上。气相hs是含钨前体物质和含硅前体物质。气相中含硅前体化合物与含钨前体化合物的摩尔比选择为大于500。

2. 发明授权

US07199414B2 Stress-reduced layer system for use in storage capacitors 失效
标题翻译：用于存储电容器的应力降低层系统
公开(公告)号：US07199414B2
公开(公告)日：2007-04-03
申请号：US10780075
申请日：2004-02-17
申请人： Matthias Goldbach , Bernhard Sell , Annette Sänger
发明人： Matthias Goldbach , Bernhard Sell , Annette Sänger
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087 , H01L27/10852 , H01L27/10861
摘要： The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.
摘要翻译：应力降低层系统具有至少一个第一层多晶或单晶半导体材料，其邻接微晶或非晶，导电或绝缘的第二层。半导体层掺杂有至少两种相同导电类型的掺杂剂，其中至少一种适用于降低界面处的机械应力。在另一实施例中，应力降低层系统具有至少一个第一半导体材料层，导电或绝缘材料以及至少一个导电或绝缘的第二层。掺杂有至少一种适合于在第二层和第一层之间的界面处降低机械应力的掺杂剂的另一半导体层被布置在第一层和第二层之间，或者被施加到与界面相对的第一层或第二层。

3. 发明授权

US06987295B2 Trench capacitor and method for fabricating the trench capacitor 失效
标题翻译：沟槽电容器和制造沟槽电容器的方法
公开(公告)号：US06987295B2
公开(公告)日：2006-01-17
申请号：US10650817
申请日：2003-08-28
申请人： Bernhard Sell , Annette Sänger , Dirk Schumann
发明人： Bernhard Sell , Annette Sänger , Dirk Schumann
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/1203
摘要： A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.
摘要翻译：用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有掺杂多晶硅。每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。

4. 发明授权

US06916704B2 Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor 失效
标题翻译：用于制造沟槽电容器的上电容器电极的金属层的多次沉积
公开(公告)号：US06916704B2
公开(公告)日：2005-07-12
申请号：US10167800
申请日：2002-06-12
申请人： Martin Gutsche , Bernhard Sell , Annette Sänger , Harald Seidl
发明人： Martin Gutsche , Bernhard Sell , Annette Sänger , Harald Seidl
IPC分类号： C23C14/58 , C23C16/56 , H01L21/20 , H01L21/302 , H01L21/3205 , H01L21/334 , H01L21/44 , H01L21/461 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L29/945
摘要： An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.
摘要翻译：作为DRAM存储单元的沟槽电容器的上电容器电极，至少部分地由多个含金属层沉积在另一层之上而形成，并且在每种情况下在被沉积之后被调节。以这种方式，可以减小电极层的内应力，因此可以提高沟槽电容器的断裂强度和耐漏电流。

5. 发明授权

US06774005B2 Method for fabricating a metal carbide layer and method for fabricating a trench capacitor containing a metal carbide 有权
标题翻译：金属碳化物层的制造方法及包含金属碳化物的沟槽电容器的制造方法
公开(公告)号：US06774005B2
公开(公告)日：2004-08-10
申请号：US10206303
申请日：2002-07-26
申请人： Martin Gutsche , Peter Moll , Bernhard Sell , Annette Sänger , Harald Seidl
发明人： Martin Gutsche , Peter Moll , Bernhard Sell , Annette Sänger , Harald Seidl
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , C23C16/32 , C23C16/45525 , C23C16/56 , H01L21/28556
摘要： At least a partial layer of an upper capacitor electrode is formed by metal carbide, preferably by a transition metal carbide. In one embodiment, the metal carbide layer is formed by depositing an alternating sequence of metal-containing layers and carbon-containing layers on top of one another and then subjecting them to a heat treatment, in such a manner that they mix with one another. The patterning of the layer sequence can be carried out before the carbide formation step.
摘要翻译：上部电容器电极的至少一部分层由金属碳化物形成，优选由过渡金属碳化物形成。在一个实施方案中，金属碳化物层通过在彼此顶部沉积含金属层和含碳层的交替序列形成，然后使它们以彼此混合的方式进行热处理。层序列的图案化可以在碳化物形成步骤之前进行。

6. 发明授权

US07129173B2 Process for producing and removing a mask layer 有权
标题翻译：掩模层的制造和除去方法
公开(公告)号：US07129173B2
公开(公告)日：2006-10-31
申请号：US10649411
申请日：2003-08-27
申请人： Heike Drummer , Franz Kreupl , Annette Sänger , Manfred Engelhardt , Bernhard Sell , Peter Thieme
发明人： Heike Drummer , Franz Kreupl , Annette Sänger , Manfred Engelhardt , Bernhard Sell , Peter Thieme
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/30625 , H01L21/31144 , H01L21/76819
摘要： A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.
摘要翻译：提供半导体衬底，其上布置有第一层，第二层和第三层。第三层例如是用于图案化第二层的抗蚀剂掩模。第二层例如是用于图案化第一层的图案化硬掩模。然后，去除第三层，并沉积第四层。第四层例如是填充已经形成在第一层中的沟槽的绝缘体。然后，通过CMP步骤对第四层进行平面化。继续进行平面化，并且第二层（例如硬掩模）与第四层一起从第一层去除。第四层保持在布置在第一层中的沟槽中的适当位置。

7. 发明授权

US06998307B2 Method for fabricating a storage capacitor 失效
公开(公告)号：US06998307B2
公开(公告)日：2006-02-14
申请号：US10650055
申请日：2003-08-26
申请人： Bernhard Sell , Annette Sänger , Dirk Schumann
发明人： Bernhard Sell , Annette Sänger , Dirk Schumann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/28518 , H01L21/31604 , H01L27/10814 , H01L28/60
摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

8. 发明授权

US07273790B2 Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
标题翻译：用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元
公开(公告)号：US07273790B2
公开(公告)日：2007-09-25
申请号：US10901406
申请日：2004-07-27
申请人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sänger
发明人： Stephan Kudelka , Martin Popp , Harald Seidl , Annette Sänger
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.
摘要翻译：在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

9. 发明授权

US06686265B2 Method of producing a capacitor electrode with a barrier structure 有权
标题翻译：制造具有阻挡结构的电容器电极的方法
公开(公告)号：US06686265B2
公开(公告)日：2004-02-03
申请号：US10127618
申请日：2002-04-22
申请人： Gerhard Beitel , Annette Sänger , Igor Kasko
发明人： Gerhard Beitel , Annette Sänger , Igor Kasko
IPC分类号： H01L2144
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/31053 , H01L21/3212 , H01L27/10852 , H01L28/55 , H01L28/75
摘要： A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.
摘要翻译：制造具有下面的阻挡结构的电容器电极。使用屏障结合层，并采用CMP（化学机械抛光）工艺以产生阻挡结构。具有下面的阻挡结构的电容器电极通过在半导体衬底上沉积阻挡层来制造; 用光刻掩模和蚀刻步骤从阻挡层形成阻挡结构; 沉积覆盖阻挡结构和周围区域的势垒结合层; 并通过化学机械抛光去除阻挡层结合层，直到阻挡结构未被覆盖，从而在阻挡结构之上形成电容器电极。

10. 发明授权

US07078309B2 Methods for producing a structured metal layer 失效
公开(公告)号：US07078309B2
公开(公告)日：2006-07-18
申请号：US09734467
申请日：2000-12-11
申请人： Gerhard Beitel , Annette Sänger , Walter Hartner
发明人： Gerhard Beitel , Annette Sänger , Walter Hartner
IPC分类号： H01L21/20
CPC分类号： C23C16/409 , H01L21/3212 , H01L28/55 , H01L28/60 , H01L28/75
摘要： The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of conventional slurries such as are already used to structure non-precious metals. Owing to the formation of an alloy, the chemically active components of the slurry are capable of attacking the additive to the precious metal in the alloy, as a result of which the surface of the alloy layer is roughened and the mechanical removal of the precious metal is increased.

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