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1. 发明授权

US5857090A Input/output subsystem having an integrated advanced programmable interrupt controller for use in a personal computer 失效
标题翻译：具有用于个人计算机的集成高级可编程中断控制器的输入/输出子系统
公开(公告)号：US5857090A
公开(公告)日：1999-01-05
申请号：US581162
申请日：1995-12-29
申请人： Barry R. Davis , Bruce Young
发明人： Barry R. Davis , Bruce Young
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A computer system is described having one or more host processors, a host chipset and a input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host chipset is connected to the input/output subsystem by a primary personal computer interface (PCI) bus. The I/O subsystem is connected to I/O devices by a secondary PCI bus. The I/O subsystem includes advanced programmable interrupt controller (APIC) functionality typically provided within an I/O APIC chip within a host chipset. The APIC functionality of the I/O subsystem is primarily implemented in software executing on a core processor of the I/O subsystem. The software creates and accesses various APIC registers and tables, such as a redirection table, within a memory of the I/O subsystem. A single 3-wire APIC bus interconnects the host processors with the I/O subsystem. With this arrangement, non-PCI interrupt lines from the I/O devices are connected only into the I/O subsystem, rather than into the host chipset.
摘要翻译：描述了具有一个或多个主机处理器，主机芯片组和输入/输出（I / O）子系统的计算机系统。主处理器通过主机总线连接到主机芯片组。主机芯片组通过主要个人计算机接口（PCI）总线连接到输入/输出子系统。 I / O子系统通过辅助PCI总线连接到I / O设备。 I / O子系统包括通常在主机芯片组内的I / O APIC芯片内提供的高级可编程中断控制器（APIC）功能。 I / O子系统的APIC功能主要是在I / O子系统的核心处理器上执行的软件中实现的。该软件在I / O子系统的存储器内创建和访问各种APIC寄存器和表，如重定向表。单个3线APIC总线将主机处理器与I / O子系统互连。通过这种安排，来自I / O设备的非PCI中断线仅连接到I / O子系统中，而不是连接到主机芯片组中。

2. 发明授权

US09313328B2 Active call processing and notifications 有权
公开(公告)号：US09313328B2
公开(公告)日：2016-04-12
申请号：US12234596
申请日：2008-09-19
申请人： Vlad Vendrow , Bruce Young
发明人： Vlad Vendrow , Bruce Young
IPC分类号： H04M3/493
CPC分类号： H04M3/493
摘要： Embodiments of the invention relate generally to computing devices and systems, as well as software, computer programs, applications, and user interfaces, and more particularly, to processing active calls and stored calls in a communication network for packetized and/or synchronous communications, and to generating notifications relating to active calls and stored calls. Other embodiments relate to creating and implementing bypass rules that allow a party to bypass a set of default prompts to a the party's communication device while enabling the caller device to access functions of a call processing system.

3. 发明申请

US20130082134A1 Document Processing Apparatus Component, Document Processing Apparatus Assembly and Method for Operating the Same 审中-公开
标题翻译：文件处理装置部件，文件处理装置及其操作方法
公开(公告)号：US20130082134A1
公开(公告)日：2013-04-04
申请号：US13250140
申请日：2011-09-30
申请人： Johan P. Bakker , Michael J. Moore , Bruce Young , Robert D. Klein , Sandra J. Korell
发明人： Johan P. Bakker , Michael J. Moore , Bruce Young , Robert D. Klein , Sandra J. Korell
IPC分类号： B65H16/02 , B65H18/02
CPC分类号： B65H16/02 , B65H5/28 , B65H2301/4131 , B65H2301/544 , B65H2701/11332
摘要： A component is disclosed. The component includes a base member having an upper surface and a lower surface and a substantially tubular member attached to and extending away from the upper surface of the base member. The substantially tubular member includes a body formed by an outer surface, an inner surface, an upper lip surface connecting the outer surface to the inner surface and a document landing surface. The body includes a thickness (T) extending between the outer surface and the inner surface. The document landing surface is connected to the inner surface. The inner surface and the document landing surface define a cavity extending through a portion of a length (L) of the body. An assembly is also disclosed.
摘要翻译：公开了一个组件。该部件包括具有上表面和下表面的基部构件和附接到基部构件的上表面并远离基座构件的上表面延伸的大致管状构件。基本上管状的构件包括由外表面，内表面，将外表面连接到内表面的上唇表面和文件着陆表面形成的主体。主体包括在外表面和内表面之间延伸的厚度（T）。文件着陆面连接到内表面。内表面和文件着陆表面限定延伸穿过主体的长度（L）的一部分的空腔。还公开了一种组件。

4. 发明授权

US08384942B1 Message preview control 有权
公开(公告)号：US08384942B1
公开(公告)日：2013-02-26
申请号：US13403963
申请日：2012-02-23
申请人： Vladimir G. Shmunis , Vlad Vendrow , Bruce Young
发明人： Vladimir G. Shmunis , Vlad Vendrow , Bruce Young
IPC分类号： G06F15/00 , G06F3/12 , G06K1/00
CPC分类号： H04L51/12 , G06Q10/107 , G10L15/26 , H04N1/00307 , H04N1/00411 , H04N1/0044 , H04N2201/0093 , H04W4/12
摘要： Embodiments of the invention relate generally to computing devices and systems, as well as software, computer programs, applications, and user interfaces, and more particularly, to systems, devices and methods to facilitate message preview control. For example, the method may include generating representations for messages to present on an interface, and detecting selection of the representation for the message. Further, the method can include presenting preview information for the message, which can be an electronic facsimile. The representations for the messages can include a representation for an electronic facsimile, as well as a voice message and an email.

5. 发明申请

US20120213579A1 Stacking Adapter and Assembly Including the Same 审中-公开
标题翻译：堆叠适配器和包括其的组装
公开(公告)号：US20120213579A1
公开(公告)日：2012-08-23
申请号：US13372930
申请日：2012-02-14
申请人： George T. Spray , Michael J. Moore , Robert Klein , Johan P. Bakker , Bruce Young
发明人： George T. Spray , Michael J. Moore , Robert Klein , Johan P. Bakker , Bruce Young
IPC分类号： F16B17/00
CPC分类号： F16B5/0635 , Y10T403/70 , Y10T403/7045
摘要： A stacking adapter is disclosed. The stacking adapter includes a lower surface, an outer upper surface arranged opposite an inner upper surface, an outer peripheral sidewall surface that connects the outer upper surface to the lower surface, and an inner peripheral sidewall surface that connects the inner upper surface to the lower surface. An assembly is also disclosed.
摘要翻译：公开了一种堆叠适配器。堆叠适配器包括下表面，与内上表面相对布置的外上表面，将外上表面连接到下表面的外周侧壁表面和将内上表面连接到下表面的内周侧壁表面表面。还公开了一种组件。

6. 发明授权

US08134727B1 Message preview control 有权
公开(公告)号：US08134727B1
公开(公告)日：2012-03-13
申请号：US11998150
申请日：2007-11-27
申请人： Vladimir G. Shmunis , Vlad Vendrow , Bruce Young
发明人： Vladimir G. Shmunis , Vlad Vendrow , Bruce Young
IPC分类号： G06F15/00 , G06F3/12 , G06K1/00
CPC分类号： H04L51/12 , G06Q10/107 , G10L15/26 , H04N1/00307 , H04N1/00411 , H04N1/0044 , H04N2201/0093 , H04W4/12
摘要： Embodiments of the invention relate generally to computing devices and systems, as well as software, computer programs, applications, and user interfaces, and more particularly, to systems, devices and methods to facilitate message preview control. For example, the method may include generating representations for messages to present on an interface, and detecting selection of the representation for the message. Further, the method can include presenting preview information for the message, which can be an electronic facsimile. The representations for the messages can include a representation for an electronic facsimile, as well as a voice message and an email.

7. 发明申请

US20070022261A1 Method of interleaving asymmetric memory arrays 审中-公开
标题翻译：交错非对称存储器阵列的方法
公开(公告)号：US20070022261A1
公开(公告)日：2007-01-25
申请号：US11184704
申请日：2005-07-19
申请人： Bruce Young
发明人： Bruce Young
IPC分类号： G06F13/28
CPC分类号： G06F13/1647 , G06F12/0607 , G11C8/04
摘要： A method of interleaving asymmetric memory arrays for providing more uniform memory access performance in computer systems utilizing asymmetrical memory configurations. The method of interleaving asymmetric memory arrays includes grouping a quantity of memory devices into a paired set and one unpaired device if the quantity of memory devices present is an odd number; interleaving the paired set of memory devices to form an initially interleaved set; and interleaving the unpaired device with the initially interleaved set to form a finally interleaved set of memory devices if the quantity of memory devices present is an odd number.
摘要翻译：交错非对称存储器阵列的方法，用于在利用不对称存储器配置的计算机系统中提供更均匀的存储器访问性能。交织非对称存储器阵列的方法包括：如果存在的存储器件的数量是奇数，则将一定数量的存储器件分组成成对组和一个未配对器件; 交织所述成对的存储器件集合以形成最初交织的集合; 以及如果所存储的存储器件的数量是奇数，则将所述未成对设备与所述初始交织集合交织以形成最后交织的存储器件集合。

8. 发明授权

US6079022A Method and apparatus for dynamically adjusting the clock speed of a bus depending on bus activity 失效
标题翻译：根据总线活动动态调整总线时钟速度的方法和装置
公开(公告)号：US6079022A
公开(公告)日：2000-06-20
申请号：US728716
申请日：1996-10-11
申请人： Bruce Young
发明人： Bruce Young
IPC分类号： G06F1/08 , G06F1/32 , G06F13/00
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , Y02B60/1217 , Y02B60/32
摘要： A dynamic clock control comprising an idle detector and a variable speed clock supply. The idle detector detects when an idle condition appears on the bus and sends an appropriate control signal to the variable speed clock supply. The clock supply, which supplies clocking signals for the bus components coupled to the bus, changes the frequency of the clocking signals from a faster, full-speed frequency to a lower frequency. When the bus becomes active, the idle detector causes the clock supply to supply clocking signals at the original full-speed frequency. With the apparatus and method of the present invention, the frequency of the clocking signals supplied to the bus components can be dynamically controlled without user intervention. Since for many bus components, power consumption is proportional to clocking frequency, a significant power savings is obtained for the overall bus system.
摘要翻译：动态时钟控制包括空闲检测器和可变速度时钟源。空闲检测器检测总线上何时出现空闲状况，并向可变速度时钟电源发送适当的控制信号。为连接到总线的总线组件提供时钟信号的时钟电源将时钟信号的频率从更快的全速频率改变到较低的频率。当总线激活时，空闲检测器使时钟电源以原始全速频率提供时钟信号。利用本发明的装置和方法，可以动态地控制提供给总线组件的时钟信号的频率，而无需用户干预。由于对于许多总线组件，功耗与时钟频率成比例，因此总体总线系统获得了显着的功率节省。

9. 发明授权

US5771387A Method and apparatus for interrupting a processor by a PCI peripheral across an hierarchy of PCI buses 失效
标题翻译：用于通过PCI总线层级的PCI外围设备中断处理器的方法和装置
公开(公告)号：US5771387A
公开(公告)日：1998-06-23
申请号：US621128
申请日：1996-03-21
申请人： Bruce Young , Norm Rasmussen , Brad Hosler
发明人： Bruce Young , Norm Rasmussen , Brad Hosler
IPC分类号： G06F13/24 , G06F13/40 , G06F9/46
CPC分类号： G06F13/4027 , G06F13/24
摘要： A number of remote I/O ICUs, enhanced PCI--PCI bridges, and an ICC bus interface unit are distributively provided to a computer system having a processor and an hierarchy of PCI buses for facilitating PCI agents coupled to the lower level PCI buses to interrupt the processor during operation. The remote I/O ICUs, the enhanced functions of the PCI--PCI bridges, and the ICC bus interface unit advantageously leverage the PCI--PCI bridges' conventional ability in handling PCI type 1 configuration write transactions, to facilitate interrupt delivery and end of interrupt notification, by employing two specially defined PCI type 1 configuration write transactions, one for interrupt messages and another for end-of-interrupt (EOI) messages.
摘要翻译：多个远程I / O ICU，增强型PCI-PCI桥接器和ICC总线接口单元分布式提供给具有处理器和PCI总线层级的计算机系统，以便于耦合到较低级PCI总线的PCI代理中断处理器在运行。远程I / O ICU，PCI-PCI桥接器的增强功能和ICC总线接口单元有利地利用PCI-PCI桥接器处理PCI 1类配置写事务的常规能力，以促进中断传递和中断结束通过采用两个特别定义的PCI 1型配置写入事务，一个用于中断消息，另一个用于中断终止（EOI）消息。

10. 发明授权

US5727217A Circuit and method for emulating the functionality of an advanced programmable interrupt controller 失效
标题翻译：用于模拟高级可编程中断控制器功能的电路和方法
公开(公告)号：US5727217A
公开(公告)日：1998-03-10
申请号：US576511
申请日：1995-12-20
申请人： Bruce Young
发明人： Bruce Young
IPC分类号： G06F13/24 , G06F9/46 , G06F9/455
CPC分类号： G06F13/24
摘要： An Advanced Programmable Interrupt Controller ("APIC") unit utilizing an emulation processor to emulate the operations of a conventional hardware-based APIC. Emulation software executed by the emulation processor handles actual interrupt handling and allows the APIC unit to support any number of interrupt inputs within the bounds of APIC architecture. The APIC unit further comprises actual APIC bus interface circuitry coupling the APIC unit to an APIC bus and redirection tables stored in local memory on-board the emulation processor or external.
摘要翻译：利用仿真处理器来模拟传统的基于硬件的APIC的操作的高级可编程中断控制器（“APIC”）单元。由仿真处理器执行的仿真软件处理实际的中断处理，并允许APIC单元支持APIC架构范围内的任意数量的中断输入。 APIC单元还包括将APIC单元耦合到APIC总线的实际APIC总线接口电路以及存储在仿真处理器或外部的本地存储器中的重定向表。

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