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1. 发明申请

US20060057789A1 Method for manufacturing semiconductor device 失效
公开(公告)号：US20060057789A1
公开(公告)日：2006-03-16
申请号：US11266259
申请日：2005-11-04
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

2. 发明授权

US07214558B2 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US07214558B2
公开(公告)日：2007-05-08
申请号：US11257060
申请日：2005-10-25
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L21/00 , H01L21/8235
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译：提供了改进双极晶体管的性质的技术。具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜，随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

3. 发明授权

US06649458B2 Method for manufacturing semiconductor device with hetero junction bipolar transistor 有权
标题翻译：具有异质结双极晶体管的半导体器件的制造方法
公开(公告)号：US06649458B2
公开(公告)日：2003-11-18
申请号：US10347806
申请日：2003-01-22
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译：本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。因此，可以减少工时，并且可以降低半导体器件的制造成本。

4. 发明授权

US07378690B2 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US07378690B2
公开(公告)日：2008-05-27
申请号：US11727246
申请日：2007-03-26
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译：提供了改进双极晶体管的性质的技术。具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜，随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从衬底的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

5. 发明申请

US20070176207A1 Method for forming patterns on a semiconductor device using a lift off technique 失效
公开(公告)号：US20070176207A1
公开(公告)日：2007-08-02
申请号：US11727246
申请日：2007-03-26
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L31/00
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

6. 发明申请

US20070059853A1 Method for Manufacturing Semiconductor Device 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20070059853A1
公开(公告)日：2007-03-15
申请号：US11554952
申请日：2006-10-31
申请人： Atsushi KUROKAWA , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi KUROKAWA , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21/00
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译：本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。因此，可以减少工时，并且可以降低半导体器件的制造成本。

7. 发明授权

US07029938B2 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US07029938B2
公开(公告)日：2006-04-18
申请号：US10809525
申请日：2004-03-26
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L21/00 , H01L21/8238
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of gold germanium, nickel and Au in this order over the entire surface of a substrate, so that the resulting stacked film will not become an isolated pattern. Thus, the stacked film over the base mesa is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa. Generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material which hardly reacts with an n-type GaAs layer or n-type InGaAs layer.
摘要翻译：通过剥离法在集电体周围形成集电体电极时，在区域OA1的外周与形成有基台面的区域之间的连接部分上形成抗蚀剂膜，接着形成金，锗，金等，从而使得所得到的层叠膜不会成为隔离图案。因此，基底台面上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面上的剥离。通过使用几乎不与n型GaAs层或n型InGaAs层反应的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻。

8. 发明申请

US20060032762A1 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US20060032762A1
公开(公告)日：2006-02-16
申请号：US11257060
申请日：2005-10-25
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： B65D75/00
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译：提供了改进双极晶体管的性质的技术。具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜，随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

9. 发明授权

US06867079B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06867079B2
公开(公告)日：2005-03-15
申请号：US10673374
申请日：2003-09-30
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L29/872 , H01L21/3205 , H01L21/329 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L23/52 , H01L27/04 , H01L27/06 , H01L29/47 , H01L29/737 , H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译：本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。因此，可以减少工时，并且可以降低半导体器件的制造成本。

10. 发明授权

US07132320B2 Method for manufacturing semiconductor device 失效
公开(公告)号：US07132320B2
公开(公告)日：2006-11-07
申请号：US11266259
申请日：2005-11-04
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

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