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1. 发明申请

US20060136854A1 Method for placement of pipeline latches 审中-公开
标题翻译：放置管道锁存器的方法
公开(公告)号：US20060136854A1
公开(公告)日：2006-06-22
申请号：US11017993
申请日：2004-12-21
申请人： Andreas Arp , Markus Buehler , Martin Eckert , Juergen Pille
发明人： Andreas Arp , Markus Buehler , Martin Eckert , Juergen Pille
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F17/5031
摘要： An integrated chip die comprises a data source connected to a data sink by way of a signal path wherein one or more pipeline latches are automatically inserted into the signal path at predetermined intervals when the length of the signal path is greater than a predetermined maximum signal propagation length.
摘要翻译：集成芯片管芯包括通过信号路径连接到数据宿的数据源，其中当信号路径的长度大于预定的最大信号传播时，其中一个或多个流水线锁存器以预定间隔自动插入到信号路径中长度。

2. 发明授权

US06341093B1 SOI array sense and write margin qualification 失效
标题翻译： SOI阵列感和写裕度资格
公开(公告)号：US06341093B1
公开(公告)日：2002-01-22
申请号：US09872885
申请日：2001-06-01
申请人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/41
摘要： The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
摘要翻译：本发明涉及存储装置，特别涉及用于测试历史依赖存储器阵列单元的存储质量的方法。可以用预定的测试条件选择性地对电池进行应力，使得这些测试条件覆盖当电池在全部工作条件下操作时可能出现的所有硬件状态分布。这主要通过切断有效字线选择脉冲的后沿的预定截止宽度来实现。

3. 发明授权

US07092310B2 Memory array with multiple read ports 失效
标题翻译：具有多个读端口的内存阵列
公开(公告)号：US07092310B2
公开(公告)日：2006-08-15
申请号：US11010902
申请日：2004-12-13
申请人： Martin Eckert , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Juergen Pille , Dieter Wendel
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C8/16
摘要： A multiport array comprises a read section which is separated from an array of memory cells and which forms a plurality of data-out ports each consisting of a predetermined number of output lines. The read section comprises a multiplex network containing a plurality of multiplex arrays each associated with one of the data-out ports (0,1, . . . ,15). The multiplex arrays are connected to the data read lines of the memory cells and are selected by read addresses. The multiplex arrays comprise transmission elements which connect selected ones of the data read lines to the associated data-out port.
摘要翻译：多端口阵列包括与存储器单元阵列分离并且形成多个数据输出端口的读取部件，每个数据输出端口由预定数量的输出线路组成。读取部分包括多路复用网络，该多路复用网络包含多个多路复用阵列，每个多路复用阵列与数据输出端口（0,1，...，15）之一相关联。多路复用阵列连接到存储单元的数据读取线，并通过读地址进行选择。多路复用阵列包括将选定数据读取线连接到相关联的数据输出端口的传输元件。

4. 发明申请

US20050135179A1 Memory array with multiple read ports 失效
标题翻译：具有多个读端口的内存阵列
公开(公告)号：US20050135179A1
公开(公告)日：2005-06-23
申请号：US11010902
申请日：2004-12-13
申请人： Martin Eckert , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Juergen Pille , Dieter Wendel
IPC分类号： G11C7/10 , G11C8/00 , G11C8/16
CPC分类号： G11C7/1075 , G11C8/16
摘要： A multiport array comprises a read section which is separated from an array of memory cells and which forms a plurality of data-out ports each consisting of a predetermined number of output lines. The read section comprises a multiplex network containing a plurality of multiplex arrays each associated with one of the data-out ports (0,1, . . . ,15). The multiplex arrays are connected to the data read lines of the memory cells and are selected by read addresses. The multiplex arrays comprise transmission elements which connect selected ones of the data read lines to the associated data-out port.
摘要翻译：多端口阵列包括与存储器单元阵列分离并且形成多个数据输出端口的读取部件，每个数据输出端口由预定数量的输出线路组成。读取部分包括多路复用网络，该多路复用网络包含多个多路复用阵列，每个多路复用阵列与数据输出端口（0,1，...，15）之一相关联。多路复用阵列连接到存储单元的数据读取线，并通过读地址进行选择。多路复用阵列包括将选定数据读取线连接到相关联的数据输出端口的传输元件。

5. 发明授权

US08535956B2 Chip attach frame 失效
标题翻译：芯片连接架
公开(公告)号：US08535956B2
公开(公告)日：2013-09-17
申请号：US13396207
申请日：2012-02-14
申请人： Martin Eckert , Otto Torreiter , Quintino L. Trianni
发明人： Martin Eckert , Otto Torreiter , Quintino L. Trianni
IPC分类号： G01R31/26
CPC分类号： H01L24/75 , G01R1/0466 , G01R1/0483 , H01L21/4853 , H01L21/67144 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/75252 , H01L2224/75301 , H01L2224/75315 , H01L2224/75316 , H01L2224/75501 , H01L2224/757 , H01L2224/75754 , H01L2224/75756 , H01L2224/759 , H01L2224/81121 , H01L2224/81136 , H01L2224/81191 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/81908 , H05K13/0413 , Y10T29/53178 , H01L2924/00014 , H01L2924/014 , H01L2924/00012
摘要： A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.
摘要翻译：芯片连接框架用于将集成电路芯片的引脚与芯片载体上的焊盘对齐。框架块具有限定形成参考角的两个对齐边缘的套筒。芯片下降到插座中，芯片载体倾斜，同时支撑框架块和芯片，直到芯片在重力作用下移动到参考角。一旦位于参考角处，通过在x和y方向上移动框架块来仔细调整芯片位置，直到引脚与焊盘对准。框架块被弹簧偏压以防止在x和y方向上移动，并且使用指旋螺钉来调节框架块的位置。一旦引脚与焊盘对准，就可以使用柱塞机构来固定集成电路芯片与芯片载体的强制接合。

6. 发明申请

US20120169485A1 Industrial Tool 审中-公开
标题翻译：工业工具
公开(公告)号：US20120169485A1
公开(公告)日：2012-07-05
申请号：US13337199
申请日：2011-12-26
申请人： Martin Eckert
发明人： Martin Eckert
IPC分类号： G08C19/12
CPC分类号： B25B21/00 , B25B23/14 , B25F5/00
摘要： An industrial and electrically driven tool includes two mutually independent radio modules so that a redundant communication link to a controller can be set up.
摘要翻译：工业和电动工具包括两个相互独立的无线电模块，使得可以建立到控制器的冗余通信链路。

7. 发明授权

US08180142B2 Test fail analysis on VLSI chips 失效
标题翻译： VLSI芯片测试故障分析
公开(公告)号：US08180142B2
公开(公告)日：2012-05-15
申请号：US12326166
申请日：2008-12-02
申请人： Martin Eckert , Georg Goecke , Marta Junginger , Klaus Kempter , Markus Ulbricht
发明人： Martin Eckert , Georg Goecke , Marta Junginger , Klaus Kempter , Markus Ulbricht
IPC分类号： G06K9/03
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.
摘要翻译：通过选择，计算和/或呈现信息的方法提供常见测试失败签名和过程相关测试失败的紧凑图形表示。输入可以是从芯片和/或晶片处理失败的被测器件的样本的失败测试的列表。确定失败的测试，然后可以确定同时失败的其他测试。提供了几个图形输出，包括测试失败和测试失败和进程失败之间的所有可能的组合。依赖关系作为排序的二维位图打印，这些位图是使用颜色代码的结果的紧凑表示。提供了两个独立位图的减法，这消除了通用属性，并且强调了多个位图之间的差异，这允许快速识别两个不同位图之间的差异的过程失败，这两个不同的位图表示所选择的一个测试失败的潜在根本原因。

8. 发明授权

US08126703B2 Method, spoken dialog system, and telecommunications terminal device for multilingual speech output 有权
标题翻译：方法，口语对话系统和电话终端设备，用于多语言语音输出
公开(公告)号：US08126703B2
公开(公告)日：2012-02-28
申请号：US12374666
申请日：2007-07-18
申请人： Fred Runge , Klaus-Dieter Liedtke , Detlef Hardt , Martin Eckert , Wiebke Johannsen , Roman Englert
发明人： Fred Runge , Klaus-Dieter Liedtke , Detlef Hardt , Martin Eckert , Wiebke Johannsen , Roman Englert
IPC分类号： G06F17/20
CPC分类号： H04M3/493 , G06F17/289 , G10L15/22 , H04M2203/2061
摘要： A method for providing multilingual speech output in an automated spoken dialog system includes setting up a connection between a telecommunications terminal device and the spoken dialog system. In response to a connection setup, a multilingual speech output is provided that includes an output of a first speech sequence in a first language and at least one second speech sequence in at least one second language different from the first language. The first speech sequence and the at least one second speech sequence are output, at least in part, simultaneously.
摘要翻译：一种用于在自动语音对话系统中提供多语言语音输出的方法包括建立电信终端设备和口语对话系统之间的连接。响应于连接设置，提供多语言语音输出，其包括第一语言的第一语音序列的输出和不同于第一语言的至少一种第二语言的至少一个第二语音序列。第一语音序列和至少一个第二语音序列至少部分地同时输出。

9. 发明申请

US20080162146A1 METHOD AND DEVICE FOR CLASSIFYING SPOKEN LANGUAGE IN SPEECH DIALOG SYSTEMS 有权
标题翻译：用于在语音对话系统中分类语音语言的方法和设备
公开(公告)号：US20080162146A1
公开(公告)日：2008-07-03
申请号：US11949341
申请日：2007-12-03
申请人： Martin Eckert , Roman Englert , Wiebke Johannsen , Fred Runge , Markus Van Ballegooy
发明人： Martin Eckert , Roman Englert , Wiebke Johannsen , Fred Runge , Markus Van Ballegooy
IPC分类号： G10L11/00
CPC分类号： G10L15/22 , G10L15/005
摘要： A method and device are provided for classifying at least two languages in an automatic dialogue system, which processes digitized speech input. At least one speech recognition method and at least one language identification method are used on the digitized speech input in order, by logical evaluation of the results of the method, to identify the language of the speech input.
摘要翻译：提供了一种用于在自动对话系统中分类至少两种语言的方法和装置，其处理数字化语音输入。在数字化语音输入中依次使用至少一种语音识别方法和至少一种语言识别方法，通过逻辑评估方法的结果来识别语音输入的语言。

10. 发明授权

US07051609B2 Transmission mechanism comprising a shifting device 失效
标题翻译：变速机构包括换档装置
公开(公告)号：US07051609B2
公开(公告)日：2006-05-30
申请号：US10701866
申请日：2003-11-06
申请人： Martin Zimmermann , Holger Stork , Georg Schneider , Klaus Henneberger , Martin Eckert , Gunter Hirt , Thomas Jäger , Martin Vornehm , Volker Kretz-Busch , Reinhard Berger
发明人： Martin Zimmermann , Holger Stork , Georg Schneider , Klaus Henneberger , Martin Eckert , Gunter Hirt , Thomas Jäger , Martin Vornehm , Volker Kretz-Busch , Reinhard Berger
IPC分类号： F16H59/00 , F16H61/00 , F16H63/00 , G06F17/00 , G06F19/00
CPC分类号： F16H61/28 , F16H59/68 , F16H59/70 , F16H61/2807 , F16H61/32 , F16H2059/6823 , F16H2061/0053 , F16H2061/0087 , F16H2061/283 , F16H2342/02 , Y10T74/18368 , Y10T74/19251 , Y10T477/65 , Y10T477/6933 , Y10T477/75
摘要： A transmission system including a shift mechanism for operating and controlling the transmission system. To automatically detect geometric characteristic values of the transmission system or of the shifting device a selector motor and a shift motor actuate a selector finger that is displaceably mounted in a selection-shift-passageway layout. Starting from an initial position whose coordinates within the selection-shift-passageway layout are unknown, the selector finger is displaced in the directions of shifting and in the directions of selection in order to detect paths of movement in the direction of selection or shifting. The selector finger is repeatedly displaced to establish the maximum paths of movement until the predetermined transmission geometric characteristic values are completely detected. Also disclosed are a control device for controlling a transmission system that includes a shift mechanism, and a method for controlling such a transmission system.
摘要翻译：一种传输系统，包括用于操作和控制传输系统的移位机构。为了自动检测传动系统或换档装置的几何特征值，选择器马达和换档马达驱动可选择地安装在选择换档通道布局中的选择指。从选择位移通道布局中的坐标未知的初始位置开始，选择手指沿着移动方向和选择方向移位，以便检测在选择或移位方向上的移动路径。选择手指重复移位以建立最大的移动路径，直到完全检测到预定的传输几何特征值。还公开了一种用于控制包括移位机构的传输系统的控制装置，以及用于控制这种传输系统的方法。

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