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1. 发明授权

US06905919B2 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension 有权
标题翻译：用垫锁体延伸形成部分耗尽的绝缘体硅（PDSOI）晶体管的方法
公开(公告)号：US06905919B2
公开(公告)日：2005-06-14
申请号：US10628913
申请日：2003-07-29
申请人： Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
发明人： Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.
摘要翻译：已经开发了在绝缘体上硅层上形成的MOSFET器件结构以及用于制造所述MOSFET器件结构的工艺顺序。该工艺具有在MOSFET器件结构的特定位置形成的绝缘体填充的浅沟槽隔离（STI）区域，用于降低栅极结构结下方的寄生晶体管形成的风险。在形成“T”形或“H”形栅极结构之后，形成与STI区域和栅极结构的部件相邻的第一导电类型的主体接触区域。接下来进行位于相同STI区域的相反侧的第二导电类型的源极/漏极区域的形成以及相同的栅极结构部件。通过存在分离的STI区域可以防止通过体接触区域和源极/漏极区域发生在栅极结构下方的不需要的寄生晶体管形成。

2. 发明授权

US06998682B2 Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension 有权
标题翻译：用垫锁体延伸形成部分耗尽的绝缘体硅（PDSOI）晶体管的方法
公开(公告)号：US06998682B2
公开(公告)日：2006-02-14
申请号：US11128010
申请日：2005-05-12
申请人： Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
发明人： Yeen Tat Chan , Kheng Chok Tee , Yiang Aun Nga , Zhao Lun , Wang Ling Goh , Diing Shenp Ang
IPC分类号： H01L27/01
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.
摘要翻译：已经开发了在绝缘体上硅层上形成的MOSFET器件结构以及用于制造所述MOSFET器件结构的工艺顺序。该工艺具有在MOSFET器件结构的特定位置形成的绝缘体填充的浅沟槽隔离（STI）区域，用于降低栅极结构结下方的寄生晶体管形成的风险。在形成“T”形或“H”形栅极结构之后，形成与STI区域和栅极结构的部件相邻的第一导电类型的主体接触区域。接下来进行位于相同STI区域的相反侧的第二导电类型的源极/漏极区域的形成以及相同的栅极结构部件。通过存在分离的STI区域可以防止通过体接触区域和源极/漏极区域发生在栅极结构下方的不需要的寄生晶体管形成。

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