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1. 发明申请

US20130234228A1 ERASABLE PROGRAMMABLE SINGLE-PLOY NONVOLATILE MEMORY 有权
标题翻译：可擦除可编程的单槽非易失性存储器
公开(公告)号：US20130234228A1
公开(公告)日：2013-09-12
申请号：US13572731
申请日：2012-08-13
申请人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L27/115
CPC分类号： H01L27/11558 , G11C16/0433 , G11C2216/10 , H01L29/42328 , H01L29/7883 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

2. 发明授权

US08592886B2 Erasable programmable single-ploy nonvolatile memory 有权
标题翻译：可擦除可编程单态非易失性存储器
公开(公告)号：US08592886B2
公开(公告)日：2013-11-26
申请号：US13572731
申请日：2012-08-13
申请人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
发明人： Te-Hsun Hsu , Hsin-Ming Chen , Ching-Sung Yang , Wen-Hao Ching , Wei-Ren Chen
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L27/11558 , G11C16/0433 , G11C2216/10 , H01L29/42328 , H01L29/7883 , H01L29/7885
摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.
摘要翻译：可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮动栅极晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同栅氧化层。

3. 发明授权

US08587036B2 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US08587036B2
公开(公告)日：2013-11-19
申请号：US12333315
申请日：2008-12-12
申请人： Shih-Chen Wang , Wen-Hao Ching
发明人： Shih-Chen Wang , Wen-Hao Ching
IPC分类号： H01L29/788
CPC分类号： H01L27/11558 , H01L27/11517 , H01L27/11519
摘要： A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
摘要翻译：在基板上形成非易失性存储器。非易失性存储器包括隔离结构，浮动栅极和栅极电介质层。隔离结构设置在基板中以限定有源区域。浮动栅极设置在基板上并且跨过有效区域。栅极电介质层设置在浮置栅极和衬底之间。浮动栅极包括第一区域和第二区域。第二区域的能带低于第一区域的能带，使得存储在浮置栅极中的电荷远离浮置栅极和栅极电介质层的重叠区域。

4. 发明授权

US08456916B2 Non-volatile memory unit cell with improved sensing margin and reliability 有权
标题翻译：非易失性存储单元，具有改进的感测裕度和可靠性
公开(公告)号：US08456916B2
公开(公告)日：2013-06-04
申请号：US13541755
申请日：2012-07-04
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
摘要翻译：唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

5. 发明授权

US08089798B2 Method for operating one-time programmable read-only memory 有权
标题翻译：一次性可编程只读存储器的操作方法
公开(公告)号：US08089798B2
公开(公告)日：2012-01-03
申请号：US12627244
申请日：2009-11-30
申请人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
发明人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
IPC分类号： G11C17/00
CPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
摘要翻译：提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过第二掺杂区域和第一掺杂区域和衬底处于参考电压。

6. 发明申请

US20110310669A1 Logic-Based Multiple Time Programming Memory Cell 有权
标题翻译：基于逻辑的多时间编程存储单元
公开(公告)号：US20110310669A1
公开(公告)日：2011-12-22
申请号：US12818095
申请日：2010-06-17
申请人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
发明人： Wen-Hao Ching , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , G11C2216/10 , H01L27/11519 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.
摘要翻译：非易失性存储器系统包括一个或多个非易失性存储器单元。每个非易失性存储单元包括浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。耦合装置位于第一导电区域中。第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。第二浮栅晶体管位于第三导电区域中。这种非易失性存储单元还包括两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

7. 发明申请

US20100148238A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20100148238A1
公开(公告)日：2010-06-17
申请号：US12333315
申请日：2008-12-12
申请人： Shih-Chen Wang , Wen-Hao Ching
发明人： Shih-Chen Wang , Wen-Hao Ching
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11558 , H01L27/11517 , H01L27/11519
摘要： A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
摘要翻译：在基板上形成非易失性存储器。非易失性存储器包括隔离结构，浮动栅极和栅极电介质层。隔离结构设置在基板中以限定有源区域。浮动栅极设置在基板上并且跨越有效区域。栅极电介质层设置在浮置栅极和衬底之间。浮动栅极包括第一区域和第二区域。第二区域的能带低于第一区域的能带，使得存储在浮置栅极中的电荷远离浮置栅极和栅极电介质层的重叠区域。

8. 发明申请

US20100073985A1 METHOD FOR OPERATING ONE-TIME PROGRAMMABLE READ-ONLY MEMORY 有权
标题翻译：一次性可编程只读存储器的操作方法
公开(公告)号：US20100073985A1
公开(公告)日：2010-03-25
申请号：US12627244
申请日：2009-11-30
申请人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
发明人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
IPC分类号： G11C17/08
CPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.
摘要翻译：提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过第二掺杂区域和第一掺杂区域和衬底处于参考电压。

9. 发明申请

US20080296701A1 ONE-TIME PROGRAMMABLE READ-ONLY MEMORY 审中-公开
标题翻译：一次性可编程只读存储器
公开(公告)号：US20080296701A1
公开(公告)日：2008-12-04
申请号：US11956633
申请日：2007-12-14
申请人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
发明人： Tsung-Mu Lai , Shao-Chang Huang , Wen-hao Ching , Chun-Hung Lu , Shih-Chen Wang , Ming-Chou Ho
IPC分类号： H01L27/112
CPC分类号： H01L27/112 , G11C17/16 , G11C17/18 , H01L27/11206
摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect.
摘要翻译：一种包括衬底，第一掺杂区域，第二掺杂区域，栅极电介质层，第一栅极和第二栅极的可编程只读存储器（OTP-ROM）。衬底是第一导电类型。第一掺杂区域和第二掺杂区域是第二导电类型，并且分别设置在衬底中。栅电介质层设置在第一掺杂区和第二掺杂区之间的衬底上。第一栅极和第二栅极分别设置在栅极介电层上。第一栅极与第一掺杂区相邻，而第二栅极与第二掺杂区相邻。这里，第一个栅极电耦合接地，OTP-ROM通过击穿效应进行编程。

10. 发明授权

US08705289B2 Flash memory apparatus with programming voltage control generators 有权
标题翻译：带编程电压控制发生器的闪存设备
公开(公告)号：US08705289B2
公开(公告)日：2014-04-22
申请号：US13344621
申请日：2012-01-06
申请人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
发明人： Ching-Sung Yang , Wen-Hao Ching , Wei-Ming Ku , Yung-Hsiang Chen , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/12
摘要： A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cells and a plurality of programming voltage control generators. Each of the memory cells receives a programming control voltage through a control end thereof, and executes data programming operation according to the programming control voltages. Each of the programming voltage control generators includes a pre-charge voltage transmitter and a pumping capacitor. The pre-charge voltage transmitter provides pre-charge voltage to the end of each of the corresponding memory cells according to pre-charge enable signal during a first period. A pumping voltage is provided to the pumping capacitor during a second period, and the programming control voltage is generated at the control end of each of the memory cells.
摘要翻译：提供一种闪存装置。闪存装置包括多个存储单元和多个编程电压控制发生器。每个存储单元通过其控制端接收编程控制电压，并根据编程控制电压执行数据编程操作。每个编程电压控制发生器包括预充电电压发射器和泵浦电容器。预充电电压发射器在第一时段期间根据预充电使能信号向每个相应存储器单元的末端提供预充电电压。在第二时段期间向泵浦电容器提供泵浦电压，并且在每个存储器单元的控制端产生编程控制电压。

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