专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07916519B2 Burn-in methods for static random access memories and chips 有权
标题翻译：静态随机存取存储器和芯片的老化方法
公开(公告)号：US07916519B2
公开(公告)日：2011-03-29
申请号：US12368218
申请日：2009-02-09
申请人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
发明人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C11/41 , G11C29/025
摘要： A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.
摘要翻译：一种SRAM和芯片的老化方法。对于SRAM的存储单元，SRAM老化方法控制存储器单元的控制信号，以产生通过存储单元，对应位线和相应位线条的电流路径。通过提供老化电流流过电流路径来测试电流路径中的触点/通孔，从而使不匹配的触点/通孔被老化电流烧毁。老化测试失败的SRAM在老化过程之后被放弃。

2. 发明申请

US20100202219A1 BURN-IN METHODS FOR STATIC RANDOM ACCESS MEMORIES AND CHIPS 有权
标题翻译：用于静态随机存取存储器和存储器的烧录方法
公开(公告)号：US20100202219A1
公开(公告)日：2010-08-12
申请号：US12368218
申请日：2009-02-09
申请人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
发明人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/02 , G11C11/41 , G11C29/025
摘要： A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure.
摘要翻译：一种SRAM和芯片的老化方法。对于SRAM的存储单元，SRAM老化方法控制存储器单元的控制信号，以产生通过存储单元，对应位线和相应位线条的电流路径。通过提供老化电流流过电流路径来测试电流路径中的触点/通孔，从而使不匹配的触点/通孔被老化电流烧毁。老化测试失败的SRAM在老化过程之后被放弃。

3. 发明申请

US20100177556A1 ASYMMETRIC STATIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：不对称静态随机存取存储器
公开(公告)号：US20100177556A1
公开(公告)日：2010-07-15
申请号：US12351772
申请日：2009-01-09
申请人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
发明人： Jui-Lung Chen , Wei-Shung Chen , Yi-Hsun Chung , Chia-Chiuan Chang
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter.
摘要翻译：提供了包括至少一个SRAM单元的非对称静态随机存取存储器（SRAM）器件。 SRAM单元包括第一反相器和第二反相器。第一反相器耦合在第一功率和地功率之间，并且包括耦合到第一节点的第一输出端和耦合到第二节点的第一输入端。第二反相器耦合在第一电源和地电之间，并且包括耦合到第一节点的第二输入端和耦合到第二节点的第二输出端。当第一逆变器和第二逆变器从第一功率接收电流时，根据第一逆变器和第二逆变器的不同电导电平，预先将SRAM单元编程为预定值。

4. 发明申请

US20090141534A1 DETECTION APPARATUS AND METHOD FOR SEQUENTIALLY PROGRAMMING MEMORY 审中-公开
标题翻译：用于顺序编程存储器的检测装置和方法
公开(公告)号：US20090141534A1
公开(公告)日：2009-06-04
申请号：US12191129
申请日：2008-08-13
申请人： Chia-Chiuan CHANG , Jui-Lung Chen , Yi-Hsun Chung , Wei-Shung Chen
发明人： Chia-Chiuan CHANG , Jui-Lung Chen , Yi-Hsun Chung , Wei-Shung Chen
IPC分类号： G11C17/16 , G11C7/00 , G11C8/00
CPC分类号： G11C5/143 , G11C8/08 , G11C17/18
摘要： A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory cell and generates a control signal according to the detection result. The programming controller is coupled to the current sensor. The programming controller receives the control signal and generates a programming state signal.
摘要翻译：提供了一种用于顺序编程存储器的检测装置。检测装置包括电流传感器和编程控制器。电流传感器耦合到编程源和存储器单元。电流传感器检测编程电源和存储单元之间的编程电流的变化，并根据检测结果生成控制信号。编程控制器耦合到电流传感器。编程控制器接收控制信号并产生编程状态信号。

5. 发明授权

US07706203B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07706203B2
公开(公告)日：2010-04-27
申请号：US12191116
申请日：2008-08-13
申请人： Jui-Lung Chen , Yi-Hsun Chung , Chia-Chiuan Chang , Wei-Shung Chen
发明人： Jui-Lung Chen , Yi-Hsun Chung , Chia-Chiuan Chang , Wei-Shung Chen
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C8/08
摘要： A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.
摘要翻译：提供一种存储器系统，包括至少一个存储器单元和源极电源电路。每个存储器单元耦合在源电压和接地电压之间，并根据字线信号和位线信号访问数字数据。源电源电路将源电压提供给存储器单元。当存储器单元处于写入状态时，源电压是第一个电源电压。当存储器单元处于读取状态时，源电压是第二个电源电压。第二电源电压等于由特定电压减去的第一个电源电压，以避免重写错误。

6. 发明申请

US20090238023A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20090238023A1
公开(公告)日：2009-09-24
申请号：US12191116
申请日：2008-08-13
申请人： Jui-Lung CHEN , Yi-Hsun Chung , Chia-Chiuan Chang , Wei-Shung Chen
发明人： Jui-Lung CHEN , Yi-Hsun Chung , Chia-Chiuan Chang , Wei-Shung Chen
IPC分类号： G11C5/14 , G11C8/08
CPC分类号： G11C11/417 , G11C5/147 , G11C8/08
摘要： A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error.
摘要翻译：提供一种存储器系统，包括至少一个存储器单元和源极电源电路。每个存储器单元耦合在源电压和接地电压之间，并根据字线信号和位线信号访问数字数据。源电源电路将源电压提供给存储器单元。当存储器单元处于写入状态时，源电压是第一个电源电压。当存储器单元处于读取状态时，源电压是第二个电源电压。第二电源电压等于由特定电压减去的第一个电源电压，以避免重写错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式