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1. 发明授权

US08921918B2 Three-dimensional semiconductor devices 有权
标题翻译：三维半导体器件
公开(公告)号：US08921918B2
公开(公告)日：2014-12-30
申请号：US13280759
申请日：2011-10-25
申请人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
发明人： Jae-Joo Shim , Kyoung-Hoon Kim , Woonkyung Lee , Wonseok Cho , Hoosung Cho , Jintaek Park , Jong-Yeon Kim , Sung-Min Hwang
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region.
摘要翻译：可以提供三维半导体器件。这些装置可以包括包括栅极图案和绝缘图案的堆叠结构。堆叠结构还可以包括第一部分和第二部分，并且堆叠结构的第二部分可以具有比第一部分更窄的宽度。装置还可以包括穿透堆叠结构的活动图案。所述装置还可以包括与堆栈结构相邻的公共源区。所述装置还可以包括在公共源区上的捆扎接触塞。

2. 发明授权

US08564050B2 3D semiconductor devices and methods of fabricating same 有权
标题翻译： 3D半导体器件及其制造方法
公开(公告)号：US08564050B2
公开(公告)日：2013-10-22
申请号：US13297493
申请日：2011-11-16
申请人： Sang-Yong Park , Jintaek Park , Hansoo Kim , Juhyuck Chung , Wonseok Cho
发明人： Sang-Yong Park , Jintaek Park , Hansoo Kim , Juhyuck Chung , Wonseok Cho
IPC分类号： H01L29/66
CPC分类号： H01L21/823475 , H01L27/11519 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.
摘要翻译：三维（3D）半导体器件包括：垂直通道，其从靠近基板的下端延伸到上端并连接多个存储单元;以及包括所述多个单元的单元阵列，其中所述单元阵列布置在具有台阶的层的栅堆叠中结构设置在基板上。栅极堆叠包括下层，其包括耦合到靠近下端的下部非存储晶体管的下部选择线，上层包括分别耦合到靠近上端的上部非存储晶体管的导线，并作为单个导电片连接以形成上部选择线，以及分别包括字线并耦合到单元晶体管的中间层，其中中间层设置在下部选择线和上部选择线之间。

3. 发明授权

US08394716B2 Methods of manufacturing three-dimensional semiconductor devices and related devices 有权
标题翻译：制造三维半导体器件及相关器件的方法
公开(公告)号：US08394716B2
公开(公告)日：2013-03-12
申请号：US12963241
申请日：2010-12-08
申请人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
发明人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
IPC分类号： H01L21/44
CPC分类号： H01L21/768 , H01L23/5226 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.
摘要翻译：三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面离衬底更远。多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。还讨论了相关方法。

4. 发明申请

US20120322252A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY 有权
标题翻译：包含三维存储器单元阵列的半导体存储器件
公开(公告)号：US20120322252A1
公开(公告)日：2012-12-20
申请号：US13594102
申请日：2012-08-24
申请人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
发明人： Byoungkeun SON , Hansoo Kim , Youngsoo An , Mingu Kim , Jinho Kim , Jaehyoung Choi , Sukhun Choi , Jae-Joo Shim , Wonseok Cho , Sunil Shim , Ju-Young Lim
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , G11C7/18 , H01L23/535 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
摘要翻译：半导体存储器件包括基本上平面的衬底; 垂直于衬底的存储器串，所述存储器串包括多个存储单元; 和多个细长字线，每个字线包括基本上平行于衬底并连接到存储器串的第一部分和相对于衬底基本上倾斜并在衬底上延伸的第二部分，其中多个字线电连接到设置在存储器串的第一侧的第一导线，并且多个字线的第二组电连接到设置在存储器串的第二侧的第二导电线。

5. 发明申请

US20110180941A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20110180941A1
公开(公告)日：2011-07-28
申请号：US13012485
申请日：2011-01-24
申请人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
发明人： Sung-Min Hwang , Hansoo Kim , Wonseok Cho , Jaehoon Jang
IPC分类号： H01L23/52 , H01L21/28
CPC分类号： H01L21/768 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.
摘要翻译：提供一种三维半导体器件及其制造方法。该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

6. 发明申请

US20110147801A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US20110147801A1
公开(公告)日：2011-06-23
申请号：US12953748
申请日：2010-11-24
申请人： Jae-Joo SHIM , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
发明人： Jae-Joo SHIM , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
IPC分类号： H01L27/06
CPC分类号： H01L23/3157 , H01L21/76816 , H01L23/291 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
摘要翻译：提供一种三维半导体器件及其制造方法。三维半导体器件可以包括用于提供间隙区域的模具结构和包括布置在间隙区域中的多个互连图案的互连结构。模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

7. 发明申请

US20100109065A1 THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES 有权
标题翻译：具有分包活性棒的三维非易失性存储器件及其制造方法
公开(公告)号：US20100109065A1
公开(公告)日：2010-05-06
申请号：US12612125
申请日：2009-11-04
申请人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
发明人： Jin-Yong Oh , Woonkyung Lee , Jin-Sung Lee , Sunil Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Jin-Soo Lim
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11565 , H01L27/11582
摘要： Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.
摘要翻译：提供非易失性存储器件和制造这种器件的方法。在该方法中，导电层和绝缘层交替堆叠在基板上。形成第一子活动杆，其穿过导电层的第一子集和绝缘层的第一子集。第一子活性棒与衬底电连接。形成第二子活动杆，其穿透导电层的第二子集和绝缘层的第二子集。第二子活动杆电连接到第一子活动杆。第二副活性杆的底部的宽度小于第二副活性杆的顶部的宽度。

8. 发明申请

US20090315095A1 Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof 有权
标题翻译：多层非易失性存储器件，采用这种器件的存储器系统及其制造方法
公开(公告)号：US20090315095A1
公开(公告)日：2009-12-24
申请号：US12456391
申请日：2009-06-16
申请人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
发明人： Jonghyuk Kim , Han-Soo Kim , YoungSeop Rah , Min-sung Song , Jang Young Chul , Soon-Moon Jung , Wonseok Cho
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/82385 , H01L21/8221 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L23/481 , H01L23/485 , H01L27/0688 , H01L27/11526 , H01L27/11551 , H01L2224/9202 , H01L21/76898
摘要： In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.
摘要翻译：在多层存储器件中，采用该器件的存储器系统和形成这种器件的方法在第一存储器件层上的第二存储器件层包括包括第二存储单元区域的第二衬底。第二衬底仅包括第二存储单元区域中的单个阱，第二存储单元区域的单阱包括掺杂有第一类型和第二类型之一杂质的半导体材料。单阱限定了第二衬底的第二存储单元区域中的有源区。多个第二电池串被布置在第二有源区域中的第二衬底上。虽然第二存储单元区域仅包括单个阱，但是在第二层的存储单元的编程或擦除操作期间，需要向第二层的衬底中的单个阱施加高电压，高电压将不妨碍第一层，第二层或其它层的外围晶体管的操作，因为它们彼此隔离。结果，第二层的基底可以被制备成具有更薄的轮廓，并且具有更少的加工步骤，导致具有更高密度，更高可靠性和降低制造成本的装置。

9. 发明授权

US08742466B2 Three-dimensional semiconductor device including a mold structure providing gap regions and an interconnection structure including a plurality of interconnection patterns formed in the gap regions 有权
标题翻译：三维半导体器件包括提供间隙区域的模具结构和包括形成在间隙区域中的多个互连图案的互连结构
公开(公告)号：US08742466B2
公开(公告)日：2014-06-03
申请号：US12953748
申请日：2010-11-24
申请人： Jae-Joo Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
发明人： Jae-Joo Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
IPC分类号： H01L23/52
CPC分类号： H01L23/3157 , H01L21/76816 , H01L23/291 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
摘要翻译：提供一种三维半导体器件及其制造方法。三维半导体器件可以包括用于提供间隙区域的模具结构和包括设置在间隙区域中的多个互连图案的互连结构。模具结构可以包括限定互连图案的上表面和下表面的层间模具和限定层间模具下面的互连图案的侧壁的侧壁模具。

10. 发明申请

US20130313629A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：三维半导体存储器件及其制造方法
公开(公告)号：US20130313629A1
公开(公告)日：2013-11-28
申请号：US13830208
申请日：2013-03-14
申请人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
发明人： Sunil Shim , Jaehoon Jang , Hansoo Kim , Sungmi Hwang , Wonseok Cho , Jinsoo Lim
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11556 , H01L27/11582
摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.
摘要翻译：一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器层，形成导电图案。

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