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1. 发明申请

US20130272071A1 DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS 有权
标题翻译：确定记忆细胞组合的软数据
公开(公告)号：US20130272071A1
公开(公告)日：2013-10-17
申请号：US13444443
申请日：2012-04-11
申请人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
发明人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

2. 发明授权

US08395939B2 Compensation of back pattern effect in a memory device 有权
标题翻译：在存储器件中补偿背面图案效果
公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

3. 发明申请

US20120307566A1 MEMORY CELL SENSING USING A BOOST VOLTAGE 有权
标题翻译：使用升压电压进行记忆细胞感测
公开(公告)号：US20120307566A1
公开(公告)日：2012-12-06
申请号：US13151456
申请日：2011-06-02
申请人： Violante Moschiano , Domenico Di Cicco , Andrea D'Alessandro
发明人： Violante Moschiano , Domenico Di Cicco , Andrea D'Alessandro
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3436
摘要： The present disclosure includes devices, methods, and systems including memory cell sensing using a boost voltage. One or more embodiments include pre-charging and/or floating a data line associated with a selected memory cell, boosting the pre-charged and/or floating data line, and determining a state of the selected memory cell based on a sensed discharge of the data line after boosting the data line.
摘要翻译：本公开包括包括使用升压电压的存储器单元感测的装置，方法和系统。一个或多个实施例包括预先充电和/或浮动与所选择的存储器单元相关联的数据线，升压预充电和/或浮置数据线，以及基于感测到的放电，确定所选择的存储器单元的状态提升数据线后的数据线。

4. 发明申请

US20120300549A1 MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS 有权
标题翻译：存储器件页面缓冲器配置和方法
公开(公告)号：US20120300549A1
公开(公告)日：2012-11-29
申请号：US13572854
申请日：2012-08-13
申请人： Paul D. Ruby , Violante Moschiano
发明人： Paul D. Ruby , Violante Moschiano
IPC分类号： G11C16/04
CPC分类号： G11C14/0018 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.
摘要翻译：描述了包括存储器阵列中的页缓冲器之间的通信电路的存储器件和方法。示例包括提供与给定页面缓冲器直接相邻的页面缓冲器的状态信息的通信电路。交换的信息可以用于调整给定的页面缓冲器以补偿在同时操作的直接相邻数据线中的效果。

5. 发明授权

US08233329B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

6. 发明授权

US08174897B2 Programming in a memory device 有权
标题翻译：在存储设备中进行编程
公开(公告)号：US08174897B2
公开(公告)日：2012-05-08
申请号：US13170420
申请日：2011-06-28
申请人： Violante Moschiano , Marco-Domenico Tiburzi , Giovanni Santin , Giulio G. Marotta
发明人： Violante Moschiano , Marco-Domenico Tiburzi , Giovanni Santin , Giulio G. Marotta
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译：提供了用于编程存储器件和存储器件的方法。根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。

7. 发明申请

US20110058424A1 DATA LINE MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：存储器件中的数据线管理
公开(公告)号：US20110058424A1
公开(公告)日：2011-03-10
申请号：US12556941
申请日：2009-09-10
申请人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
发明人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
摘要： Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.
摘要翻译：公开了存储器件和方法，例如被配置为在程序操作的第一部分期间向数据线施加第一程序禁止偏置的器件，并且在程序操作的第二部分期间对数据线施加第二程序禁止偏置。第二个程序禁止偏置大于第一个程序抑制偏置。

8. 发明申请

US20100157685A1 PROGRAMMING IN A MEMORY DEVICE 有权
标题翻译：在存储设备中编程
公开(公告)号：US20100157685A1
公开(公告)日：2010-06-24
申请号：US12477314
申请日：2009-06-03
申请人： Violante Moschiano , Marco-Domenico Tiburzi , Giovanni Santin , Giulio G. Marotta
发明人： Violante Moschiano , Marco-Domenico Tiburzi , Giovanni Santin , Giulio G. Marotta
IPC分类号： G11C16/04
CPC分类号： G11C16/3454
摘要： Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
摘要翻译：提供了用于编程存储器件，存储器件和存储器系统的方法。根据至少一种这样的方法，通过一系列编程脉冲对所选存储单元进行编程。一系列编程脉冲被配置为编程脉冲，其中每组具有相同的脉冲量，并且组中的每个编程脉冲具有基本上相同的幅度（即编程电压）。后续组的编程脉冲的幅度通过来自先前振幅的阶跃电压而增加。

9. 发明申请

US20090290426A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20090290426A1
公开(公告)日：2009-11-26
申请号：US12123765
申请日：2008-05-20
申请人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
发明人： Violante Moschiano , Daniel Elmhurst , Giovanni Santin
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译：在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元在编程的第一页分发。在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。第一和第二数量之间的差异表示经历快速电荷损失的电池数量。该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。

10. 发明授权

US07535787B2 Methods and apparatuses for refreshing non-volatile memory 有权
标题翻译：用于刷新非易失性存储器的方法和装置
公开(公告)号：US07535787B2
公开(公告)日：2009-05-19
申请号：US11810550
申请日：2007-06-06
申请人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
发明人： Daniel Elmhurst , Violante Moschiano , Paul Ruby
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C11/406 , G11C16/0483 , G11C2211/4062
摘要： Methods and apparatuses for refreshing non-volatile memories due to changes in memory cell charges, such as charge loss, are disclosed. Embodiments generally comprise a voltage generator to create a sub-threshold voltage for a memory state of memory cells in a block. Once the sub-threshold voltage is applied to a word line a state reader determines states of memory cells coupled to the word line. If the state reader determines that one or more of the memory cells coupled to the word line is in the memory state, despite the sub-threshold voltage, a memory refresher may program a number of memory cells in the block. Method embodiments generally comprise applying a sub-threshold voltage to a word line for a plurality of memory cells, detecting at least one memory cell of the plurality violates a state parameter, and refreshing a block of memory cells associated with the plurality of cells.
摘要翻译：公开了由于诸如电荷损失的存储器单元费用的变化而刷新非易失性存储器的方法和装置。实施例通常包括电压发生器以产生用于块中的存储器单元的存储器状态的次阈值电压。一旦子阈值电压被施加到字线，状态读取器就确定耦合到字线的存储器单元的状态。如果状态读取器确定耦合到字线的一个或多个存储器单元处于存储器状态，尽管存在子阈值电压，存储器刷新器可以对块中的多个存储单元进行编程。方法实施例通常包括将子阈值电压施加到多个存储器单元的字线，检测多个存储单元中的至少一个存储单元违反状态参数，以及刷新与多个单元相关联的存储单元块。

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