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1. 发明授权

US07952401B2 Standby control circuit and method 有权
标题翻译：待机控制电路和方法
公开(公告)号：US07952401B2
公开(公告)日：2011-05-31
申请号：US12565775
申请日：2009-09-24
申请人： Shankar Ramakrishnan , Kumar Abhishek , Ashish Goel , Ankit Gupta , Chandan Gupta , Mithlesh Shrivas , Rahul Sood
发明人： Shankar Ramakrishnan , Kumar Abhishek , Ashish Goel , Ankit Gupta , Chandan Gupta , Mithlesh Shrivas , Rahul Sood
IPC分类号： H03L7/00
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
摘要翻译：用于集成电路模块的备用控制电路包括第一控制电路，其在集成电路模块的正常操作模式下响应于指示待机模式输入事件的异步待机信号，以输出与主电源同步的待机模式信号时钟信号以指示集成电路模块的待机操作模式。备用控制电路还包括第二控制电路，其以集成电路模块的降低功率模式响应于指示待机模式输入事件的异步待机信号，以控制第一控制电路输出与指示备用操作模式的辅助时钟信号。

2. 发明授权

US06188088B1 Electrostatic discharge protection for analog switches 有权
标题翻译：模拟开关的静电放电保护
公开(公告)号：US06188088B1
公开(公告)日：2001-02-13
申请号：US09349291
申请日：1999-07-08
申请人： Shankar Ramakrishnan
发明人： Shankar Ramakrishnan
IPC分类号： H01L2972
CPC分类号： H01L27/0262 , H03K17/08142
摘要： Electrostatic discharge protection for analog switches using silicon-controlled rectifiers. Two silicon-controlled rectifiers (SCRs) may be formed in a common isolation region of an integrated circuit. Each SCR has its gate and cathode coupled together so as to be self triggering. The SCRs are connected in parallel in reverse polarity and coupled between the analog switch input or output and ground. In normal switch operation, both SCRs will be off, though when the voltage of the protected switch connection exceed on of the supply rails, one of the SCRs will trigger, providing a low impedance connection to ground. Once the voltage returns to normal, the SCR will automatically release.
摘要翻译：使用硅控整流器的模拟开关的静电放电保护。两个硅控整流器（SCR）可以形成在集成电路的公共隔离区域中。每个SCR的栅极和阴极耦合在一起，以便自我触发。 SCR以反极性并联连接，并耦合在模拟开关输入或输出与地之间。在正常的开关操作中，两个SCR都将关闭，但是当受保护的开关连接的电压超过电源轨时，其中一个SCR将触发，从而提供低阻抗的接地。一旦电压恢复正常，SCR将自动释放。

3. 发明授权

US6154085A Constant gate drive MOS analog switch 有权
标题翻译：恒闸驱动MOS模拟开关
公开(公告)号：US6154085A
公开(公告)日：2000-11-28
申请号：US149206
申请日：1998-09-08
申请人： Shankar Ramakrishnan
发明人： Shankar Ramakrishnan
IPC分类号： H03K17/00 , H03K17/06 , H03K17/62
CPC分类号： H03K17/063 , H03K2217/0018
摘要： A constant gate drive metal-oxide semiconductor ("MOS") analog switch. In one embodiment, the analog switch includes first, second, and third devices, and a level shifter. The first device includes a source coupled to an input terminal, a drain coupled to an output terminal, and a gate. The second device includes a source coupled to the input terminal, a drain, and a gate. The third device includes a source coupled to the drain of the second device, a drain coupled to the output terminal, and a gate. The level shifter includes an input coupled to the drain of the second device and an output coupled to the gates of the first, second, and third devices. The level shifter provides a constant gate drive to the first device, regardless of a signal on the input terminal, resulting in a constant on-resistance of the analog switch. In addition, a constant linearity of on-resistance is achieved by keeping the gate voltage constant with respect to the mid-point of the source and drain voltages.
摘要翻译：恒定栅极驱动金属氧化物半导体（“MOS”）模拟开关。在一个实施例中，模拟开关包括第一，第二和第三装置以及电平转换器。第一器件包括耦合到输入端子的源极，耦合到输出端子的漏极和栅极。第二装置包括耦合到输入端子，漏极和栅极的源极。第三器件包括耦合到第二器件的漏极的源极，耦合到输出端子的漏极和栅极。电平移位器包括耦合到第二器件的漏极的输入端和耦合到第一，第二和第三器件的栅极的输出。电平移位器为第一器件提供恒定栅极驱动，而不管输入端子上的信号如何，导致模拟开关的导通电阻恒定。此外，通过保持栅极电压相对于源极和漏极电压的中点恒定来实现导通电阻的恒定线性度。

4. 发明申请

US20100102865A1 STANDBY CONTROL CIRCUIT AND METHOD 有权
标题翻译：待机控制电路和方法
公开(公告)号：US20100102865A1
公开(公告)日：2010-04-29
申请号：US12565775
申请日：2009-09-24
申请人： Shankar RAMAKRISHNAN , Kumar ABHISHEK , Ashish GOEL , Ankit GUPTA , Chandan GUPTA , Mithlesh SHRIVAS , Rahul SOOD
发明人： Shankar RAMAKRISHNAN , Kumar ABHISHEK , Ashish GOEL , Ankit GUPTA , Chandan GUPTA , Mithlesh SHRIVAS , Rahul SOOD
IPC分类号： H03K3/02
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
摘要翻译：用于集成电路模块的备用控制电路包括第一控制电路，其在集成电路模块的正常操作模式下响应于指示待机模式输入事件的异步待机信号，以输出与主电源同步的待机模式信号时钟信号以指示集成电路模块的待机操作模式。备用控制电路还包括第二控制电路，其以集成电路模块的降低功率模式响应于指示待机模式输入事件的异步待机信号，以控制第一控制电路输出与指示备用操作模式的辅助时钟信号。

5. 发明授权

US06492860B1 Low voltage CMOS analog switch 有权
标题翻译：低电压CMOS模拟开关
公开(公告)号：US06492860B1
公开(公告)日：2002-12-10
申请号：US09626013
申请日：2000-07-25
申请人： Shankar Ramakrishnan
发明人： Shankar Ramakrishnan
IPC分类号： H03K1762
CPC分类号： H03K17/6872 , H03K17/162 , H03K17/6874
摘要： A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor. In another embodiment, the second transmission gate includes a second P-channel transistor coupled in series to a second N-channel transistor coupled in series to a third P-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third P-channel transistors being coupled to the gate of the first P-channel transistor and a gate of the second N-channel transistor being coupled to the gate of the first N-channel transistor.
摘要翻译：一种低电压模拟开关，其具有低漏电截止电流，并且包括具有第一N沟道晶体管和第一P沟道晶体管的第一传输栅极，每个第一和第二晶体管具有耦合在一起的各自的漏极和源极端子，以形成开关漏极和源极端子和具有与串联连接到第三N沟道晶体管的第二P沟道晶体管串联耦合的第二N沟道晶体管的第二传输门，所述第二传输门与第一传输门并联耦合，第二和第三N沟道晶体管的栅极耦合到第一N沟道晶体管的栅极，并且第二P沟道晶体管的栅极耦合到第一P沟道晶体管的栅极。在另一个实施例中，第二传输门包括串联耦合到与第三P沟道晶体管串联耦合的第二N沟道晶体管的第二P沟道晶体管，第二传输栅极并联耦合到第一传输门，第二和第三P沟道晶体管的栅极耦合到第一P沟道晶体管的栅极，并且第二N沟道晶体管的栅极耦合到第一N沟道晶体管的栅极。

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