专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08466823B2 Cascade analog-to-digital converting system 有权
标题翻译：级联模数转换系统
公开(公告)号：US08466823B2
公开(公告)日：2013-06-18
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

2. 发明申请

US20120229313A1 ANALOG TO DIGITAL CONVERTER CIRCUIT 有权
标题翻译：模拟到数字转换器电路
公开(公告)号：US20120229313A1
公开(公告)日：2012-09-13
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
发明人： Sai-Weng SIN , He-Gong WEI , Franco MALOBERTI , Li DING , Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Seng-Pan U , Rui Paulo da Silva MARTINS
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design
摘要翻译：本发明提供一种包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计

3. 发明授权

US08427355B2 Time-interleaved pipelined-SAR analog to digital converter with low power consumption 有权
标题翻译：时间交错流水线SAR模数转换器，功耗低
公开(公告)号：US08427355B2
公开(公告)日：2013-04-23
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/38
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
摘要翻译：包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计。

4. 发明申请

US20120306679A1 N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT 有权
标题翻译： N-bit连续逼近寄存器模拟到数字转换电路
公开(公告)号：US20120306679A1
公开(公告)日：2012-12-06
申请号：US13150508
申请日：2011-06-01
申请人： Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Sai-Weng SIN , Seng-Pan U , Rui Paulo Da Silva MARTINS , Franco MALOBERTI
发明人： Yan ZHU , Chi-Hang CHAN , U-Fat CHIO , Sai-Weng SIN , Seng-Pan U , Rui Paulo Da Silva MARTINS , Franco MALOBERTI
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/466
摘要： The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
摘要翻译：本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。比较器包括第一前置放大器，第二前置放大器和动态锁存器。替代方案，比较器包括四输入前置放大器和动态锁存器。

5. 发明申请

US20120194364A1 ANALOG-TO-DIGITAL CONVERTING SYSTEM 有权
标题翻译：模拟数字转换系统
公开(公告)号：US20120194364A1
公开(公告)日：2012-08-02
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

6. 发明申请

US20100182080A1 DC-OFFSET CANCELLED PROGRAMMABLE GAIN ARRAY FOR LOW-VOLTAGE WIRELESS LAN SYSTEM AND METHOD USING THE SAME 有权
标题翻译：用于低电压无线LAN系统的DC-OFFSET取消可编程增益阵列及其使用方法
公开(公告)号：US20100182080A1
公开(公告)日：2010-07-22
申请号：US12355658
申请日：2009-01-16
申请人： Pui-In Mak , Seng-Pan U. , Rui P. Martins
发明人： Pui-In Mak , Seng-Pan U. , Rui P. Martins
IPC分类号： H03F3/00
CPC分类号： H03F3/45183 , H03F1/083 , H03F3/45475 , H03F3/45744 , H03F3/45968 , H03F2203/45212 , H03F2203/45521 , H03F2203/45526 , H03F2203/45534 , H03F2203/45644
摘要： An amplifier circuit includes a transconductance amplifier at an input side of the amplifier circuit, a transimpedance amplifier connected to an output of the transconductance amplifier, and a voltage amplifier connected to an output of the transimpedance amplifier. The transconductance amplifier and the transimpedance amplifier form a low-impedance node at an interface thereof. A feedback circuit is connected between an output of the voltage amplifier and the low-impedance node between the transconductance amplifier and the transimpedance amplifier. The transconductance amplifier, the transimpedance amplifier, and the voltage amplifier form a main amplifier stage. The feedback circuit senses an imbalance in an output of the main amplifier stage, whereby a correction signal is integrated and negatively fed back to the low-impedance node between the transconductance amplifier and the transimpedance amplifier.
摘要翻译：放大器电路包括在放大器电路的输入侧的跨导放大器，连接到跨导放大器的输出的跨阻放大器和连接到跨阻放大器的输出的电压放大器。跨导放大器和跨阻抗放大器在其接口处形成低阻抗节点。反馈电路连接在电压放大器的输出端和跨导放大器和跨阻放大器之间的低阻抗节点之间。跨导放大器，跨阻放大器和电压放大器形成主放大器级。反馈电路感测主放大器级的输出的不平衡，由此校正信号被积分并负反馈回跨导放大器和跨阻放大器之间的低阻抗节点。

7. 发明申请

US20080318534A1 TWO-STEP CHANNEL SELECTION FOR WIRELESS TRANSMITTER FRONT-ENDS 有权
标题翻译：用于无线发射机前端的两步通道选择
公开(公告)号：US20080318534A1
公开(公告)日：2008-12-25
申请号：US12203837
申请日：2008-09-03
申请人： Pui-In MAK , Seng-Pan U , Rui Paulo da Silva MARTINS
发明人： Pui-In MAK , Seng-Pan U , Rui Paulo da Silva MARTINS
IPC分类号： H04B1/02
CPC分类号： H03H11/1291 , H03D3/007 , H04B1/28
摘要： A reconfigurable multimode transmitter is disclosed, operating in accordance with a two-step channel selection. The first step provides for a fine channel selection and upconversion of a desired channel to either positive or negative IF. The second step is a coarse channel selection and upconversion of a desired channel to the RF. The receiver and transmitter can be used in a transceiver.
摘要翻译：公开了可重新配置的多模式发射器，其根据两步通道选择进行操作。第一步提供精确的通道选择和所需通道的上变频到正或负IF。第二步是对RF的期望信道的粗略信道选择和上变频。接收机和发射机可以用在收发器中。

8. 发明授权

US08344931B2 N-bits successive approximation register analog-to-digital converting circuit 有权
标题翻译： N位逐次逼近寄存器模数转换电路
公开(公告)号：US08344931B2
公开(公告)日：2013-01-01
申请号：US13150508
申请日：2011-06-01
申请人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
发明人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/466
摘要： The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
摘要翻译：本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。比较器包括第一前置放大器，第二前置放大器和动态锁存器。替代方案，比较器包括四输入前置放大器和动态锁存器。

9. 发明授权

US07948309B2 DC-offset cancelled programmable gain array for low-voltage wireless LAN system and method using the same 有权
标题翻译：用于低压无线局域网系统的直流偏移取消可编程增益阵列及其使用方法
公开(公告)号：US07948309B2
公开(公告)日：2011-05-24
申请号：US12355658
申请日：2009-01-16
申请人： Pui-In Mak , Seng-Pan U , Rui P. Martins
发明人： Pui-In Mak , Seng-Pan U , Rui P. Martins
IPC分类号： H03F3/68 , H03F1/36
CPC分类号： H03F3/45183 , H03F1/083 , H03F3/45475 , H03F3/45744 , H03F3/45968 , H03F2203/45212 , H03F2203/45521 , H03F2203/45526 , H03F2203/45534 , H03F2203/45644
摘要： An amplifier circuit includes a transconductance amplifier at an input side of the amplifier circuit, a transimpedance amplifier connected to an output of the transconductance amplifier, and a voltage amplifier connected to an output of the transimpedance amplifier. The transconductance amplifier and the transimpedance amplifier form a low-impedance node at an interface thereof. A feedback circuit is connected between an output of the voltage amplifier and the low-impedance node between the transconductance amplifier and the transimpedance amplifier. The transconductance amplifier, the transimpedance amplifier, and the voltage amplifier form a main amplifier stage. The feedback circuit senses an imbalance in an output of the main amplifier stage, whereby a correction signal is integrated and negatively fed back to the low-impedance node between the transconductance amplifier and the transimpedance amplifier.
摘要翻译：放大器电路包括在放大器电路的输入侧的跨导放大器，连接到跨导放大器的输出的跨阻放大器和连接到跨阻放大器的输出的电压放大器。跨导放大器和跨阻抗放大器在其接口处形成低阻抗节点。反馈电路连接在电压放大器的输出端和跨导放大器和跨阻放大器之间的低阻抗节点之间。跨导放大器，跨阻放大器和电压放大器形成主放大器级。反馈电路感测主放大器级的输出的不平衡，由此校正信号被积分并负反馈回跨导放大器和跨阻放大器之间的低阻抗节点。

10. 发明申请

US20100184399A1 SWITCHED CURRENT RESISTOR PROGRAMMABLE GAIN ARRAY FOR LOW-VOLTAGE WIRELESS LAN AND METHOD USING THE SAME 有权
标题翻译：用于低电压无线LAN的开关电流电阻可编程增益阵列及其使用方法
公开(公告)号：US20100184399A1
公开(公告)日：2010-07-22
申请号：US12355649
申请日：2009-01-16
申请人： Pui-In Mak , Seng-Pan U , Rui P. Martins
发明人： Pui-In Mak , Seng-Pan U , Rui P. Martins
IPC分类号： H04B1/10 , H03F3/45 , H03G3/00
CPC分类号： H03F3/45475 , H03F3/3022 , H03F3/45183 , H03F3/45928 , H03F2203/45078 , H03F2203/45082 , H03F2203/45424 , H03F2203/45528 , H03F2203/45534 , H03G1/0088 , H03G1/04 , H03G3/001
摘要： A switched current resistor (SCR) PGA for constant-bandwidth gain control includes an inverting amplifier, a feedback resistor forming a feedback loop between an output side and an input side of the inverting amplifier, and a switched current resistor (SCR) array connected in parallel to the feedback resistor, and configured to tune a gain range between a maximum and a minimum. The SCR array includes a plurality of switched resistors, each comprising a switch in series with a resistor. When the plurality of switched resistors are switched by a gain-control logic, a plurality of switched current sources and a plurality of grounded resistors are switched correspondingly to deliver a transient current, an equivalent of which flows through the plurality of grounded resistors out from the input side of the inverting amplifier, leading to a feedback factor of the PGA being constant.
摘要翻译：用于恒定带宽增益控制的开关电流电阻器（SCR）PGA包括反相放大器，在反相放大器的输出侧和输入侧之间形成反馈环路的反馈电阻器，以及连接在开关电流电阻器平行于反馈电阻，并且被配置为调节最大和最小之间的增益范围。 SCR阵列包括多个开关电阻器，每个开关电阻器包括与电阻器串联的开关。当通过增益控制逻辑切换多个开关电阻器时，相应地切换多个开关电流源和多个接地电阻器，以提供瞬时电流，其瞬态电流流过多个接地电阻器反相放大器的输入侧，导致PGA的反馈因数恒定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式